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P89LPC9331/9341/9351/9361
8-bit microcontroller with accelerated two-clock 80C51 core, 4 kB/8 kB/16 kB 3 V byte-erasable flash with 8-bit ADCs
Rev. 5 -- 10 January 2011 Product data sheet
1. General description
The P89LPC9331/9341/9351/9361 is a single-chip microcontroller, available in low cost packages, based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system-level functions have been incorporated into the P89LPC9331/9341/9351/9361 in order to reduce component count, board space, and system cost.
2. Features and benefits
2.1 Principal features
4 kB/8 kB/16 kB byte-erasable flash code memory organized into 1 kB sectors and 64-byte pages. Single-byte erasing allows any byte(s) to be used as non-volatile data storage. 256-byte RAM data memory. P89LPC9351 and P89LPC9361 also include a 512-byte auxiliary on-chip RAM. 512-byte customer data EEPROM on-chip allows serialization of devices, storage of setup parameters, etc. (P89LPC9351/9361) Dual 4-input multiplexed 8-bit ADC/DAC outputs. Two analog comparators with selectable inputs and reference source. Dual Programmable Gain Amplifiers (PGA) with selectable gains of 2x, 4x, 8x, or 16x can be applied to ADCs and analog comparator inputs. (P89LPC9351/9361) On-chip temperature sensor integrated with ADC module. Two 16-bit counter/timers (each may be configured to toggle a port output upon timer overflow or to become a PWM output). A 23-bit system timer that can also be used as a real-time clock consisting of a 7-bit prescaler and a programmable and readable 16-bit timer. Enhanced UART with a fractional baud rate generator, break detect, framing error detection, and automatic address detection; 400 kHz byte-wide I2C-bus communication port and SPI communication port. Capture/Compare Unit (CCU) provides PWM, input capture, and output compare functions. (P89LPC9351/9361) 2.4 V to 3.6 V VDD operating range. I/O pins are 5 V tolerant (may be pulled up or driven to 5.5 V). Enhanced low voltage (brownout) detect allows a graceful system shutdown when power fails. 28-pin TSSOP and PLCC packages with 23 I/O pins minimum and up to 26 I/O pins while using on-chip oscillator and reset options.
NXP Semiconductors
P89LPC9331/9341/9351/9361
8-bit microcontroller with accelerated two-clock 80C51 core
2.2 Additional features
A high performance 80C51 CPU provides instruction cycle times of 111 ns to 222 ns for all instructions except multiply and divide when executing at 18 MHz. This is six times the performance of the standard 80C51 running at the same clock frequency. A lower clock frequency for the same performance results in power savings and reduced EMI. Serial flash In-Circuit Programming (ICP) allows simple production coding with commercial EPROM programmers. Flash security bits prevent reading of sensitive application programs. Serial flash In-System Programming (ISP) allows coding while the device is mounted in the end application. In-Application Programming (IAP) of the flash code memory. This allows changing the code in a running application. Watchdog timer with separate on-chip oscillator, nominal 400 kHz, calibrated to 5 %, requiring no external components. The watchdog prescaler is selectable from eight values. High-accuracy internal RC oscillator option, with clock doubler option, allows operation without external oscillator components. The RC oscillator option is selectable and fine tunable. Clock switching on the fly among internal RC oscillator, watchdog oscillator, external clock source provides optimal support of minimal power active mode with fast switching to maximum performance. Idle and two different power-down reduced power modes. Improved wake-up from Power-down mode (a LOW interrupt input starts execution). Typical power-down current is 1 A (total power-down with voltage comparators disabled). Active-LOW reset. On-chip power-on reset allows operation without external reset components. A software reset function is also available. Configurable on-chip oscillator with frequency range options selected by user programmed flash configuration bits. Oscillator options support frequencies from 20 kHz to the maximum operating frequency of 18 MHz. Oscillator fail detect. The watchdog timer has a separate fully on-chip oscillator allowing it to perform an oscillator fail detect function. Programmable port output configuration options: quasi-bidirectional, open drain, push-pull, input-only. High current sourcing/sinking (20 mA) on eight I/O pins (P0.3 to P0.7, P1.4, P1.6, P1.7). All other port pins have high sinking capability (20 mA). A maximum limit is specified for the entire chip. Port `input pattern match' detect. Port 0 may generate an interrupt when the value of the pins match or do not match a programmable pattern. Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10 ns minimum ramp times. Only power and ground connections are required to operate the P89LPC9331/9341/9351/9361 when internal reset option is selected. Four interrupt priority levels. Eight keypad interrupt inputs, plus two additional external interrupt inputs. Schmitt trigger port inputs. Second data pointer. Emulation support.
P89LPC9331_9341_9351_9361 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 -- 10 January 2011
2 of 94
NXP Semiconductors
P89LPC9331/9341/9351/9361
8-bit microcontroller with accelerated two-clock 80C51 core
3. Ordering information
Table 1. Ordering information Package Name P89LPC9331FDH P89LPC9331HDH P89LPC9341FDH P89LPC9351FA P89LPC9351FDH P89LPC9361FDH TSSOP28 TSSOP28 TSSOP28 PLCC28 TSSOP28 TSSOP28 Description plastic thin shrink small outline package; 28 leads; body width 4.4 mm plastic thin shrink small outline package; 28 leads; body width 4.4 mm plastic thin shrink small outline package; 28 leads; body width 4.4 mm plastic leaded chip carrier; 28 leads plastic thin shrink small outline package; 28 leads; body width 4.4 mm plastic thin shrink small outline package; 28 leads; body width 4.4 mm Version SOT361-1 SOT361-1 SOT361-1 SOT261-2 SOT361-1 SOT361-1 Type number
3.1 Ordering options
Table 2. Ordering options Flash memory 4 kB 4 kB 8 kB 8 kB 8 kB 16 kB Temperature range -40 C to +85 C -40 C to +125 C -40 C to +85 C -40 C to +85 C -40 C to +85 C -40 C to +85 C Frequency 0 MHz to 18 MHz 0 MHz to 18 MHz 0 MHz to 18 MHz 0 MHz to 18 MHz 0 MHz to 18 MHz 0 MHz to 18 MHz Type number P89LPC9331FDH P89LPC9331HDH P89LPC9341FDH P89LPC9351FA P89LPC9351FDH P89LPC9361FDH
P89LPC9331_9341_9351_9361
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Product data sheet
Rev. 5 -- 10 January 2011
3 of 94
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P89LPC9331/9341/9351/9361
8-bit microcontroller with accelerated two-clock 80C51 core
4. Block diagram
P89LPC9331/9341/9351/9361
ACCELERATED 2-CLOCK 80C51 CPU
4 kB/8 kB/16 kB CODE FLASH 256-BYTE DATA RAM 512-BYTE AUXILIARY RAM(1)
UART internal bus I2C-BUS
TXD RXD SCL SDA SPICLK MOSI MISO SS
SPI
512-BYTE DATA EEPROM(1) PORT 3 CONFIGURABLE I/Os PORT 2 CONFIGURABLE I/Os PORT 1 CONFIGURABLE I/Os PORT 0 CONFIGURABLE I/Os
REAL-TIME CLOCK/ SYSTEM TIMER TIMER 0 TIMER 1 T0 T1 CMP2 CIN2B CIN2A CMP1 CIN1A CIN1B OCA OCB OCC OCD ICA ICB AD10 AD11 AD12 AD13 DAC1 AD00 AD01 AD02 AD03 DAC0
P3[1:0]
P2[7:0]
ANALOG COMPARATORS
P1[7:0]
P0[7:0]
CCU (CAPTURE/ COMPARE UNIT)(1)
KEYPAD INTERRUPT WATCHDOG TIMER AND OSCILLATOR
ADC1/DAC1(2)
PROGRAMMABLE OSCILLATOR DIVIDER
CPU clock
ADC0/TEMP SENSOR/DAC0(3)
XTAL1 CRYSTAL OR RESONATOR XTAL2
CONFIGURABLE OSCILLATOR
ON-CHIP RC OSCILLATOR WITH CLOCK DOUBLER
POWER MONITOR (POWER-ON RESET, BROWNOUT RESET)
002aad555
(1) P89LPC9351/9361 (2) PGA1 on P89LPC9351/9361 (3) PGA0 on P89LPC9351/9361
Fig 1.
Block diagram
P89LPC9331_9341_9351_9361
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Product data sheet
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P89LPC9331/9341/9351/9361
8-bit microcontroller with accelerated two-clock 80C51 core
5. Functional diagram
VDD VSS
DAC1
AD01 AD10 AD11 AD12 AD13
KBI0 KBI1 KBI2 KBI3 KBI4 KBI5 KBI6 KBI7 CLKOUT
CMP2 CIN2B CIN2A CIN1B CIN1A CMPREF CMP1 T1 XTAL2
PORT 0
PORT 1
TXD RXD T0 INT0 INT1 RST AD00 AD03 AD02 MOSI MISO SS SPICLK
SCL SDA
P89LPC9331/ P89LPC9341
PORT 3
DAC0
XTAL1 PORT 2
002aae461
Fig 2.
Functional diagram (P89LPC9331/9341)
VDD
VSS
DAC1
AD01 AD10 AD11 AD12 AD13
KBI0 KBI1 KBI2 KBI3 KBI4 KBI5 KBI6 KBI7 CLKOUT
CMP2 CIN2B CIN2A CIN1B CIN1A CMPREF CMP1 T1 XTAL2
PORT 0
PORT 1
P89LPC9351/ P89LPC9361
PORT 3
TXD RXD T0 INT0 INT1 RST OCB OCC ICB OCD MOSI MISO SS SPICLK OCA ICA
SCL SDA
AD00 AD03 AD02 DAC0
XTAL1 PORT 2
002aad556
Fig 3.
Functional diagram (P89LPC9351/9361)
P89LPC9331_9341_9351_9361
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Product data sheet
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P89LPC9331/9341/9351/9361
8-bit microcontroller with accelerated two-clock 80C51 core
6. Pinning information
6.1 Pinning
P2.0/AD03/DAC0 P2.1/AD02 P0.0/CMP2/KBI0/AD01 P1.7/AD00 P1.6 P1.5/RST VSS P3.1/XTAL1 P3.0/XTAL2/CLKOUT
1 2 3 4 5 6 7 8 9
28 P2.7 27 P2.6 26 P0.1/CIN2B/KBI1/AD10 25 P0.2/CIN2A/KBI2/AD11 24 P0.3/CIN1B/KBI3/AD12 23 P0.4/CIN1A/KBI4/DAC1/AD13 22 P0.5/CMPREF/KBI5 21 VDD 20 P0.6/CMP1/KBI6 19 P0.7/T1/KBI7 18 P1.0/TXD 17 P1.1/RXD 16 P2.5/SPICLK 15 P2.4/SS
002aae462
P89LPC9331FDH/ P89LPC9341FDH
P1.4/INT1 10 P1.3/INT0/SDA 11 P1.2/T0/SCL 12 P2.2/MOSI 13 P2.3/MISO 14
Fig 4.
P89LPC9331/9341 TSSOP28 pin configuration
P2.0/ICB/DAC0/AD03 P2.1/OCD/AD02 P0.0/CMP2/KBI0/AD01 P1.7/OCC/AD00 P1.6/OCB P1.5/RST VSS P3.1/XTAL1 P3.0/XTAL2/CLKOUT
1 2 3 4 5 6 7 8 9
28 P2.7/ICA 27 P2.6/OCA 26 P0.1/CIN2B/KBI1/AD10 25 P0.2/CIN2A/KBI2/AD11 24 P0.3/CIN1B/KBI3/AD12 23 P0.4/CIN1A/KBI4/DAC1/AD13 22 P0.5/CMPREF/KBI5 21 VDD 20 P0.6/CMP1/KBI6 19 P0.7/T1/KBI7 18 P1.0/TXD 17 P1.1/RXD 16 P2.5/SPICLK 15 P2.4/SS
002aad557
P89LPC9351FDH/ P89LPC9361FDH
P1.4/INT1 10 P1.3/INT0/SDA 11 P1.2/T0/SCL 12 P2.2/MOSI 13 P2.3/MISO 14
Fig 5.
P89LPC9351/9361 TSSOP28 pin configuration
P89LPC9331_9341_9351_9361
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(c) NXP B.V. 2011. All rights reserved.
Product data sheet
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P89LPC9331/9341/9351/9361
8-bit microcontroller with accelerated two-clock 80C51 core
28 P2.7/ICA
27 P2.6/OCA
26 P0.1/CIN2B/KBI1/AD10 25 P0.2/CIN2A/KBI2/AD11 24 P0.3/CIN1B/KBI3/AD12 23 P0.4/CIN1A/KBI4/DAC1/AD13 22 P0.5/CMPREF/KBI5 21 VDD 20 P0.6/CMP1/KBI6 19 P0.7/T1/KBI7 P1.0/TXD 18
002aad558
P0.0/CMP2/KBI0/AD01
4
P1.6/OCB P1.5/RST VSS P3.1/XTAL1 P3.0/XTAL2/CLKOUT
5 6 7 8 9
P89LPC9351FA
P1.4/INT1 10 P1.3/INT0/SDA 11 P2.5/SPICLK 16 P1.2/T0/SCL 12 P2.2/MOSI 13 P2.3/MISO 14 P1.1/RXD 17 P2.4/SS 15
Fig 6.
P89LPC9351 PLCC28 pin configuration
P89LPC9331_9341_9351_9361
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3
2
1
P2.0/ICB/DAC0/AD03
P1.7/OCC/AD00
P2.1/OCD/AD02
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Product data sheet
Rev. 5 -- 10 January 2011
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P89LPC9331/9341/9351/9361
8-bit microcontroller with accelerated two-clock 80C51 core
6.2 Pin description
Table 3. Symbol Pin description Pin PLCC28, TSSOP28 P0.0 to P0.7 I/O Port 0: Port 0 is an 8-bit I/O port with a user-configurable output type. During reset Port 0 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 0 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 7.16.1 "Port configurations" and Table 12 "Static characteristics" for details. The Keypad Interrupt feature operates with Port 0 pins. All pins have Schmitt trigger inputs. Port 0 also provides various special functions as described below: P0.0/CMP2/ KBI0/AD01 3 I/O O I I P0.1/CIN2B/ KBI1/AD10 26 I/O I I I P0.2/CIN2A/ KBI2/AD11 25 I/O I I I P0.3/CIN1B/ KBI3/AD12 24 I/O I I I P0.4/CIN1A/ KBI4/DAC1/AD13 23 I/O I I O I P0.5/CMPREF/ KBI5 22 I/O I I P0.0 -- Port 0 bit 0. CMP2 -- Comparator 2 output KBI0 -- Keyboard input 0. AD01 -- ADC0 channel 1 analog input. P0.1 -- Port 0 bit 1. CIN2B -- Comparator 2 positive input B. KBI1 -- Keyboard input 1. AD10 -- ADC1 channel 0 analog input. P0.2 -- Port 0 bit 2. CIN2A -- Comparator 2 positive input A. KBI2 -- Keyboard input 2. AD11 -- ADC1 channel 1 analog input. P0.3 -- Port 0 bit 3. High current source. CIN1B -- Comparator 1 positive input B. KBI3 -- Keyboard input 3. AD12 -- ADC1 channel 2 analog input. P0.4 -- Port 0 bit 4. High current source. CIN1A -- Comparator 1 positive input A. KBI4 -- Keyboard input 4. DAC1 -- Digital-to-analog converter output 1. AD13 -- ADC1 channel 3 analog input. P0.5 -- Port 0 bit 5. High current source. CMPREF -- Comparator reference (negative) input. KBI5 -- Keyboard input 5. Type Description
P89LPC9331_9341_9351_9361
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P89LPC9331/9341/9351/9361
8-bit microcontroller with accelerated two-clock 80C51 core
Table 3. Symbol
Pin description ...continued Pin PLCC28, TSSOP28 Type Description
P0.6/CMP1/KBI6
20
I/O O I
P0.6 -- Port 0 bit 6. High current source. CMP1 -- Comparator 1 output. KBI6 -- Keyboard input 6. P0.7 -- Port 0 bit 7. High current source. T1 -- Timer/counter 1 external count input or overflow output. KBI7 -- Keyboard input 7.
P0.7/T1/KBI7
19
I/O I/O I
P1.0 to P1.7
I/O, I Port 1: Port 1 is an 8-bit I/O port with a user-configurable output type, except for [1] three pins as noted below. During reset Port 1 latches are configured in the input only mode with the internal pull-up disabled. The operation of the configurable Port 1 pins as inputs and outputs depends upon the port configuration selected. Each of the configurable port pins are programmed independently. Refer to Section 7.16.1 "Port configurations" and Table 12 "Static characteristics" for details. P1.2 to P1.3 are open drain when used as outputs. P1.5 is input only. All pins have Schmitt trigger inputs. Port 1 also provides various special functions as described below:
P1.0/TXD P1.1/RXD P1.2/T0/SCL
18 17 12
I/O O I/O I I/O I/O I/O
P1.0 -- Port 1 bit 0. TXD -- Transmitter output for serial port. P1.1 -- Port 1 bit 1. RXD -- Receiver input for serial port. P1.2 -- Port 1 bit 2 (open-drain when used as output). T0 -- Timer/counter 0 external count input or overflow output (open-drain when used as output). SCL -- I2C-bus serial clock input/output. P1.3 -- Port 1 bit 3 (open-drain when used as output). INT0 -- External interrupt 0 input. SDA -- I2C-bus serial data input/output. P1.4 -- Port 1 bit 4. High current source. INT1 -- External interrupt 1 input. P1.5 -- Port 1 bit 5 (input only). RST -- External Reset input during power-on or if selected via UCFG1. When functioning as a reset input, a LOW on this pin resets the microcontroller, causing I/O ports and peripherals to take on their default states, and the processor begins execution at address 0. Also used during a power-on sequence to force ISP mode. P1.6 -- Port 1 bit 6. High current source. OCB -- Output Compare B. (P89LPC9351/9361) P1.7 -- Port 1 bit 7. High current source. OCC -- Output Compare C. (P89LPC9351/9361) AD00 -- ADC0 channel 0 analog input.
P1.3/INT0/SDA
11
I/O I I/O
P1.4/INT1 P1.5/RST
10 6
I/O I I I
P1.6/OCB P1.7/OCC/AD00
5 4
I/O O I/O O I
P89LPC9331_9341_9351_9361
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Product data sheet
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P89LPC9331/9341/9351/9361
8-bit microcontroller with accelerated two-clock 80C51 core
Table 3. Symbol
Pin description ...continued Pin PLCC28, TSSOP28 Type Description
P2.0 to P2.7
I/O
Port 2: Port 2 is an 8-bit I/O port with a user-configurable output type. During reset Port 2 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 2 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 7.16.1 "Port configurations" and Table 12 "Static characteristics" for details. All pins have Schmitt trigger inputs. Port 2 also provides various special functions as described below:
P2.0/ICB/DAC0 /AD03
1
I/O I O I
P2.0 -- Port 2 bit 0. ICB -- Input Capture B. (P89LPC9351/9361) DAC0 -- Digital-to-analog converter output. AD03 -- ADC0 channel 3 analog input. P2.1 -- Port 2 bit 1. OCD -- Output Compare D. (P89LPC9351/9361) AD02 -- ADC0 channel 2 analog input. P2.2 -- Port 2 bit 2. MOSI -- SPI master out slave in. When configured as master, this pin is output; when configured as slave, this pin is input. P2.3 -- Port 2 bit 3. MISO -- When configured as master, this pin is input, when configured as slave, this pin is output. P2.4 -- Port 2 bit 4. SS -- SPI Slave select. P2.5 -- Port 2 bit 5. SPICLK -- SPI clock. When configured as master, this pin is output; when configured as slave, this pin is input. P2.6 -- Port 2 bit 6. OCA -- Output Compare A. (P89LPC9351/9361) P2.7 -- Port 2 bit 7. ICA -- Input Capture A. (P89LPC9351/9361) Port 3: Port 3 is a 2-bit I/O port with a user-configurable output type. During reset Port 3 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 3 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 7.16.1 "Port configurations" and Table 12 "Static characteristics" for details. All pins have Schmitt trigger inputs. Port 3 also provides various special functions as described below:
P2.1/OCD/AD02
2
I/O O I
P2.2/MOSI
13
I/O I/O
P2.3/MISO
14
I/O I/O
P2.4/SS P2.5/SPICLK
15 16
I/O I I/O I/O
P2.6/OCA P2.7/ICA P3.0 to P3.1
27 28
I/O O I/O I I/O
P3.0/XTAL2/ CLKOUT
9
I/O O O
P3.0 -- Port 3 bit 0. XTAL2 -- Output from the oscillator amplifier (when a crystal oscillator option is selected via the flash configuration. CLKOUT -- CPU clock divided by 2 when enabled via SFR bit (ENCLK -TRIM.6). It can be used if the CPU clock is the internal RC oscillator, watchdog oscillator or external clock input, except when XTAL1/XTAL2 are used to generate clock source for the RTC/system timer.
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P89LPC9331_9341_9351_9361
Product data sheet
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P89LPC9331/9341/9351/9361
8-bit microcontroller with accelerated two-clock 80C51 core
Table 3. Symbol
Pin description ...continued Pin PLCC28, TSSOP28 Type Description
P3.1/XTAL1
8
I/O I
P3.1 -- Port 3 bit 1. XTAL1 -- Input to the oscillator circuit and internal clock generator circuits (when selected via the flash configuration). It can be a port pin if internal RC oscillator or watchdog oscillator is used as the CPU clock source, and if XTAL1/XTAL2 are not used to generate the clock for the RTC/system timer. Ground: 0 V reference. Power supply: This is the power supply voltage for normal operation as well as Idle and Power-down modes.
VSS VDD
7 21
I I
[1]
Input/output for P1.0 to P1.4, P1.6, P1.7. Input for P1.5.
P89LPC9331_9341_9351_9361
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P89LPC9331/9341/9351/9361
8-bit microcontroller with accelerated two-clock 80C51 core
7. Functional description
Remark: Please refer to the P89LPC9331/9341/9351/9361 User manual for a more detailed functional description.
7.1 Special function registers
Remark: SFR accesses are restricted in the following ways:
* User must not attempt to access any SFR locations not defined. * Accesses to any defined SFR locations must be strictly for the functions for the SFRs. * SFR bits labeled `-', `0' or `1' can only be written and read as follows:
- `-' Unless otherwise specified, must be written with `0', but can return any value when read (even if it was written with `0'). It is a reserved bit and may be used in future derivatives. - `0' must be written with `0', and will return a `0' when read. - `1' must be written with `1', and will return a `1' when read.
P89LPC9331_9341_9351_9361
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Product data sheet Rev. 5 -- 10 January 2011 13 of 94
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NXP Semiconductors
Table 4. Special function registers - P89LPC9331/9341 * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB E7 ENBI0 ENBI1 ADI13 BNDI1 CLK2 E6 ENADCI0 ENADCI1 ADI12 BURST1 CLK1 E5 TMM0 TMM1 ADI11 SCC1 CLK0 E4 EDGE0 EDGE1 ADI10 SCAN1 INBND0 E3 ADCI0 ADCI1 ADI03 BNDI0 ENDAC1 E2 ENADC0 ENADC1 ADI02 BURST0 ENDAC0 E1 ADCS01 ADCS11 ADI01 SCC0 BSA1 E0H 8EH 97H A3H C0H A1H BBH ADCS00 ADCS10 ADI00 SCAN0 BSA0 Reset value LSB E0 00 00 00 00 00 00 FF 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 000x 0000 Hex Binary
Bit address ACC* ADCON0 ADCON1 ADINS ADMODA ADMODB AD0BH Accumulator A/D control register 0 A/D control register 1 A/D input select A/D mode register A A/D mode register B A/D_0 boundary high register A/D_0 boundary low register A/D_0 data register 0 A/D_0 data register 1 A/D_0 data register 2 A/D_0 data register 3 A/D_1 boundary high register A/D_1 boundary low register
8-bit microcontroller with accelerated two-clock 80C51 core
1111 1111
P89LPC9331/9341/9351/9361
AD0BL
A6H
00
0000 0000
AD0DAT0 AD0DAT1 AD0DAT2 AD0DAT3 AD1BH
C5H C6H C7H F4H C4H
00 00 00 00 FF
0000 0000 0000 0000 0000 0000 0000 0000 1111 1111
AD1BL
BCH
00
0000 0000
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Table 4. Special function registers - P89LPC9331/9341 ...continued * indicates SFRs that are bit addressable. Name AD1DAT0 AD1DAT1 AD1DAT2 AD1DAT3 AUXR1
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Product data sheet Rev. 5 -- 10 January 2011 14 of 94
P89LPC9331_9341_9351_9361
NXP Semiconductors
Description A/D_1 data register 0 A/D_1 data register 1 A/D_1 data register 2 A/D_1 data register 3 Auxiliary function register B register Baud rate generator 0 rate low Baud rate generator 0 rate high Baud rate generator 0 control Comparator 1 control register Comparator 2 control register CPU clock divide-by-M control Data pointer (2 bytes) Data pointer high
SFR Bit functions and addresses addr. MSB D5H D6H D7H F5H A2H CLKLP EBRR ENT1 ENT0 SRST 0 -
Reset value LSB Hex 00 00 00 00 DPS 00 Binary 0000 0000 0000 0000 0000 0000 0000 0000 0000 00x0
Bit address B* BRGR0[2] F0H BEH
F7
F6
F5
F4
F3
F2
F1
F0 00 00 0000 0000 0000 0000
8-bit microcontroller with accelerated two-clock 80C51 core
P89LPC9331/9341/9351/9361
BRGR1[2]
BFH
00
0000 0000
BRGCON
BDH
-
-
-
-
-
-
SBRGS
BRGEN
00[2]
xxxx xx00
CMP1 CMP2 DIVM
ACH ADH 95H
-
-
CE1 CE2
CP1 CP2
CN1 CN2
OE1 OE2
CO1 CO2
CMF1 CMF2
00[1] 00[1] 00
xx00 0000 xx00 0000 0000 0000
DPTR DPH
83H
00
0000 0000
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Table 4. Special function registers - P89LPC9331/9341 ...continued * indicates SFRs that are bit addressable. Name DPL FMADRH FMADRL FMCON Description Data pointer low Program flash address high Program flash address low Program flash control (Read) Program flash control (Write) FMDATA I2ADR Program flash data I2C-bus slave address register I2C-bus register I2DAT I2SCLH I2C-bus data register Serial clock generator/SCL duty cycle register high Serial clock generator/SCL duty cycle register low I2C-bus status register Interrupt enable 0 DAH DDH 00 0000 0000 control SFR Bit functions and addresses addr. MSB 82H E7H E6H E4H E4H E5H DBH I2ADR.6 I2ADR.5 I2ADR.4 I2ADR.3 I2ADR.2 I2ADR.1 I2ADR.0 GC BUSY FMCMD.7 FMCMD.6 FMCMD.5 FMCMD.4 HVA FMCMD.3 HVE FMCMD.2 SV FMCMD.1 OI FMCMD.0 00 00 0000 0000 0000 0000 Reset value LSB Hex 00 00 00 70 Binary 0000 0000 0000 0000 0000 0000 0111 0000
Product data sheet Rev. 5 -- 10 January 2011 15 of 94
P89LPC9331_9341_9351_9361 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved.
NXP Semiconductors
8-bit microcontroller with accelerated two-clock 80C51 core
P89LPC9331/9341/9351/9361
Bit address I2CON* D8H
DF -
DE I2EN
DD STA
DC STO
DB SI
DA AA
D9 -
D8 CRSEL 00 x000 00x0
I2SCLL
DCH
00
0000 0000
I2STAT
D9H
STA.4 AF EA EF
STA.3 AE EWDRT EE
STA.2 AD EBO ED
STA.1 AC ES/ESR EC
STA.0 AB ET1 EB
0 AA EX1 EA
0 A9 ET0 E9
0 A8 EX0 E8
F8
1111 1000
Bit address IEN0* A8H Bit address
00
0000 0000
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Table 4. Special function registers - P89LPC9331/9341 ...continued * indicates SFRs that are bit addressable. Name IEN1* Description Interrupt enable 1 Interrupt priority 0 Interrupt priority 0 high Interrupt priority 1 Interrupt priority 1 high Keypad control register Keypad interrupt mask register Keypad pattern register Port 0 SFR Bit functions and addresses addr. MSB E8H Bit address IP0* IP0H B8H B7H EAD BF FF PAD PADH EST BE PWDRT PWDRTH FE PST PSTH BD PBO PBOH FD BC PS/PSR PSH/ PSRH FC ESPI BB PT1 PT1H FB PSPI PSPIH EC BA PX1 PX1H FA PC PCH EKBI B9 PT0 PT0H F9 PKBI PKBIH PATN _SEL Reset value LSB EI2C B8 PX0 PX0H F8 PI2C PI2CH KBIF 00[1] 00[1] 00[1] 00 00x0 0000 00x0 0000 00[1] 00[1] x000 0000 x000 0000 Hex 00[1] Binary 00x0 0000
Product data sheet Rev. 5 -- 10 January 2011 16 of 94
P89LPC9331_9341_9351_9361 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved.
NXP Semiconductors
Bit address IP1* IP1H KBCON KBMASK F8H F7H 94H 86H
8-bit microcontroller with accelerated two-clock 80C51 core
xxxx xx00 0000 0000
P89LPC9331/9341/9351/9361
KBPATN
93H 87 T1/KB7 97 A7 B7 (P0M1.7) (P0M2.7) 86 CMP1 /KB6 96 A6 B6 (P0M1.6) (P0M2.6) 85 CMPREF /KB5 95 RST A5 SPICLK B5 (P0M1.5) (P0M2.5) 84 CIN1A /KB4 94 INT1 A4 SS B4 (P0M1.4) (P0M2.4) 83 CIN1B /KB3 93 INT0/SDA A3 MISO B3 (P0M1.3) (P0M2.3) 82 CIN2A /KB2 92 T0/SCL A2 MOSI B2 (P0M1.2) (P0M2.2) 81 CIN2B /KB1 91 RXD A1 B1 XTAL1 (P0M1.1) (P0M2.1) 80 CMP2 /KB0 90 TXD A0 B0 XTAL2 (P0M1.0) (P0M2.0)
FF
1111 1111
Bit address P0* 80H Bit address P1* P2* P3* P0M1 P0M2 Port 1 Port 2 Port 3 Port 0 output mode 1 Port 0 output mode 2 90H Bit address A0H Bit address B0H 84H 85H
[1]
[1]
[1]
[1]
FF[1] 00[1]
1111 1111 0000 0000
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Table 4. Special function registers - P89LPC9331/9341 ...continued * indicates SFRs that are bit addressable. Name P1M1 P1M2 P2M1 P2M2 P3M1
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Product data sheet Rev. 5 -- 10 January 2011 17 of 94
P89LPC9331_9341_9351_9361
NXP Semiconductors
Description Port 1 output mode 1 Port 1 output mode 2 Port 2 output mode 1 Port 2 output mode 2 Port 3 output mode 1 Port 3 output mode 2 Power control register Power control register A Program status word Port 0 digital input disable Reset source register RTC control RTC register high RTC register low Serial port address register Serial port address enable
SFR Bit functions and addresses addr. MSB 91H 92H A4H A5H B1H B2H 87H B5H (P1M1.7) (P1M2.7) (P2M1.7) (P2M2.7) SMOD1 RTCPD D7 CY RTCF (P1M1.6) (P1M2.6) (P2M1.6) (P2M2.6) SMOD0 D6 AC BOIF RTCS1 (P2M1.5) (P2M2.5) VCPD D5 F0 PT0AD.5 BOF RTCS0 (P1M1.4) (P1M2.4) (P2M1.4) (P2M2.4) BOI ADPD D4 RS1 PT0AD.4 POF (P1M1.3) (P1M2.3) (P2M1.3) (P2M2.3) GF1 I2PD D3 RS0 PT0AD.3 R_BK (P1M1.2) (P1M2.2) (P2M1.2) (P2M2.2) GF0 SPPD D2 OV PT0AD.2 R_WD (P1M1.1) (P1M2.1) (P2M1.1) (P2M2.1) (P3M1.1) (P3M2.1) PMOD1 SPD D1 F1 PT0AD.1 R_SF ERTC
Reset value LSB (P1M1.0) (P1M2.0) (P2M1.0) (P2M2.0) (P3M1.0) (P3M2.0) PMOD0 D0 P R_EX RTCEN 00 00
[3]
Hex D3[1] 00[1] FF[1] 00[1] 03[1] 00[1] 00 00[1]
Binary 11x1 xx11 00x0 xx00 1111 1111 0000 0000 xxxx xx11 xxxx xx00 0000 0000 0000 0000
P3M2 PCON PCONA
8-bit microcontroller with accelerated two-clock 80C51 core
P89LPC9331/9341/9351/9361
Bit address PSW* PT0AD RSTSRC RTCCON RTCH RTCL SADDR D0H F6H DFH D1H D2H D3H A9H
0000 0000 xx00 000x
60[1][6] 00[6] 00[6] 00
011x xx00 0000 0000 0000 0000 0000 0000
SADEN
B9H
00
0000 0000
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Table 4. Special function registers - P89LPC9331/9341 ...continued * indicates SFRs that are bit addressable. Name SBUF Description Serial Port data buffer register Serial port control Serial port extended status register Stack pointer SPI control register SPI status register SPI data register Timer 0 and 1 auxiliary mode Timer 0 and 1 control Timer 0 high Timer 1 high Timer 0 low Timer 1 low Timer 0 and 1 mode Internal oscillator trim register Watchdog control register SFR Bit functions and addresses addr. MSB 99H 9F SM0/FE DBMOD 9E SM1 INTLO 9D SM2 CIDIS 9C REN DBISEL 9B TB8 FE 9A RB8 BR 99 TI OE 98 RI STINT 00 00 0000 0000 0000 0000 Reset value LSB Hex xx Binary xxxx xxxx
Product data sheet Rev. 5 -- 10 January 2011 18 of 94
P89LPC9331_9341_9351_9361 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved.
NXP Semiconductors
Bit address SCON* SSTAT 98H BAH
SP SPCTL SPSTAT SPDAT TAMOD
81H E2H E1H E3H 8FH 8F TF1 8E TR1 8D TF0 T1M2 8C TR0 8B IE1 8A IT1 89 IE0 T0M2 88 IT0 SSIG SPIF SPEN WCOL DORD MSTR CPOL CPHA SPR1 SPR0 -
07 04 00 00 00
0000 0111 0000 0100 00xx xxxx
8-bit microcontroller with accelerated two-clock 80C51 core
P89LPC9331/9341/9351/9361
0000 0000 xxx0 xxx0
Bit address TCON* TH0 TH1 TL0 TL1 TMOD TRIM 88H 8CH 8DH 8AH 8BH 89H 96H
00 00 00 00 00
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
T1GATE RCCLK
T1C/T ENCLK
T1M1 TRIM.5
T1M0 TRIM.4
T0GATE TRIM.3
T0C/T TRIM.2
T0M1 TRIM.1
T0M0 TRIM.0
00
[5][6]
WDCON
A7H
PRE2
PRE1
PRE0
-
-
WDRUN
WDTOF
WDCLK
[4][6]
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Table 4. Special function registers - P89LPC9331/9341 ...continued * indicates SFRs that are bit addressable. Name WDL WFEED1 WFEED2 Description Watchdog load Watchdog feed 1 Watchdog feed 2 SFR Bit functions and addresses addr. MSB C1H C2H C3H Reset value LSB Hex FF Binary 1111 1111
Product data sheet Rev. 5 -- 10 January 2011 19 of 94
P89LPC9331_9341_9351_9361 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved.
NXP Semiconductors
[1] [2] [3] [4] [5] [6]
All ports are in input only (high-impedance) state after power-up. BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable. The RSTSRC register reflects the cause of the P89LPC9331/9341 reset except BOIF bit. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset value is x011 0000. After reset, the value is 1110 01x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset. Other resets will not affect WDTOF. On power-on reset and watchdog reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.
8-bit microcontroller with accelerated two-clock 80C51 core
The only reset sources that affect these SFRs are power-on reset and watchdog reset.
P89LPC9331/9341/9351/9361
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Product data sheet Rev. 5 -- 10 January 2011 20 of 94
P89LPC9331_9341_9351_9361 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved.
NXP Semiconductors
Table 5. Name BODCFG
Extended special function registers - P89LPC9331/9341[1] Description BOD configuration register CLOCK Control register Temperature sensor control register Real-time clock data register high SFR addr. FFC8H Bit functions and addresses MSB LSB BOICFG1 BOICFG0 Reset value Hex
[2]
Binary
CLKCON TPSCON
FFDEH FFCAH
CLKOK -
-
-
XTALWD -
CLKDBL TSEL1
FOSC2 TSEL0
FOSC1 -
FOSC0 -
[3]
00
0000 0000
RTCDATH
FFBFH
00
0000 0000
RTCDATL
Real-time clock FFBEH data register low
00
0000 0000
8-bit microcontroller with accelerated two-clock 80C51 core
[1] [2] [3]
Extended SFRs are physically located on-chip but logically located in external data memory address space (XDATA). The MOVX A,@DPTR and MOVX @DPTR,A instructions are used to access these extended SFRs. The BOICFG1/0 will be copied from UCFG1.5 and UCFG1.3 when power-on reset. CLKCON register reset value comes from UCFG1 and UCFG2. The reset value of CLKCON.2 to CLKCON.0 come from UCFG1.2 to UCFG1.0 and reset value of CLKDBL bit comes from UCFG2.7.
P89LPC9331/9341/9351/9361
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Product data sheet Rev. 5 -- 10 January 2011 21 of 94
P89LPC9331_9341_9351_9361 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved.
NXP Semiconductors
Table 6. Special function registers - P89LPC9351/9361 * indicates SFRs that are bit addressable. Name Description SFR addr. Bit address ACC* ADCON0 ADCON1 ADINS ADMODA ADMODB AD0BH AD0BL AD0DAT0 AD0DAT1 AD0DAT2 AD0DAT3 AD1BH AD1BL AD1DAT0 AD1DAT1 AD1DAT2 Accumulator A/D control register 0 A/D control register 1 A/D input select A/D mode register A A/D mode register B A/D_0 boundary high register A/D_0 boundary low register A/D_0 data register 0 A/D_0 data register 1 A/D_0 data register 2 A/D_0 data register 3 A/D_1 boundary high register A/D_1 boundary low register A/D_1 data register 0 A/D_1 data register 1 A/D_1 data register 2 E0H 8EH 97H A3H C0H A1H BBH A6H C5H C6H C7H F4H C4H BCH D5H D6H D7H ENBI0 ENBI1 ADI13 BNDI1 CLK2 ENADCI0 ENADCI1 ADI12 BURST1 CLK1 TMM0 TMM1 ADI11 SCC1 CLK0 EDGE0 EDGE1 ADI10 SCAN1 INBND0 ADCI0 ADCI1 ADI03 BNDI0 ENDAC1 ENADC0 ENADC1 ADI02 BURST0 ENDAC0 ADCS01 ADCS11 ADI01 SCC0 BSA1 ADCS00 ADCS10 ADI00 SCAN0 BSA0 Bit functions and addresses MSB E7 E6 E5 E4 E3 E2 E1 LSB E0 00 00 00 00 00 00 FF 00 00 00 00 00 FF 00 00 00 00 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 000x 0000 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 Reset value Hex Binary
8-bit microcontroller with accelerated two-clock 80C51 core
P89LPC9331/9341/9351/9361
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Table 6. Special function registers - P89LPC9351/9361 * indicates SFRs that are bit addressable. Name AD1DAT3 AUXR1 Description A/D_1 data register 3 Auxiliary function register B register Baud rate generator 0 rate low Baud rate generator 0 rate high Baud rate generator 0 control Capture compare A control register Capture compare B control register Capture compare C control register Capture compare D control register Comparator 1 control register Comparator 2 control register Data EEPROM control register Data EEPROM data register Data EEPROM address register SFR addr. F5H A2H CLKLP F7 EBRR F6 ENT1 F5 ENT0 F4 SRST F3 0 F2 F1 DPS F0 00 00 0000 0000 0000 0000 Bit functions and addresses MSB LSB Reset value Hex 00 00 Binary 0000 0000 0000 00x0
Product data sheet Rev. 5 -- 10 January 2011 22 of 94
P89LPC9331_9341_9351_9361 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved.
NXP Semiconductors
Bit address B* BRGR0[2] F0H BEH
BRGR1[2]
BFH
00
0000 0000
BRGCON
BDH
-
-
-
-
-
-
SBRGS
BRGEN
00[2]
xxxx xx00
8-bit microcontroller with accelerated two-clock 80C51 core
P89LPC9331/9341/9351/9361
CCCRA CCCRB CCCRC CCCRD CMP1 CMP2 DEECON DEEDAT DEEADR
EAH EBH ECH EDH ACH ADH F1H F2H F3H
ICECA2 ICECB2 EEIF
ICECA1 ICECB1 HVERR
ICECA0 ICECB0 CE1 CE2 ECTL1
ICESA ICESB CP1 CP2 ECTL0
ICNFA ICNFB CN1 CN2 -
FCOA FCOB FCOC FCOD OE1 OE2 EWERR1
OCMA1 OCMB1 OCMC1 OCMD1 CO1 CO2 EWERR0
OCMA0 OCMB0 OCMC0 OCMD0 CMF1 CMF2 EADR8
00 00 00 00 00[1] 00[1] 08 00 00
0000 0000 0000 0000 xxxx x000 xxxx x000 xx00 0000 xx00 0000 00001000 0000 0000 0000 0000
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Table 6. Special function registers - P89LPC9351/9361 * indicates SFRs that are bit addressable. Name DIVM Description CPU clock divide-by-M control Data pointer (2 bytes) Data pointer high Data pointer low Program flash address high Program flash address low Program flash control (Read) Program flash control (Write) FMDATA I2ADR Program flash data I2C-bus slave address register I2C-bus register I2DAT I2SCLH I2C-bus data register Serial clock generator/SCL duty cycle register high Serial clock generator/SCL duty cycle register low I2C-bus status register DAH DDH 00 0000 0000 control 83H 82H E7H E6H E4H E4H E5H DBH I2ADR.6 DF I2ADR.5 DE I2EN I2ADR.4 DD STA I2ADR.3 DC STO I2ADR.2 DB SI I2ADR.1 DA AA I2ADR.0 D9 GC D8 CRSEL 00 x000 00x0 BUSY HVA HVE SV OI 00 00 00 00 70 0000 0000 0000 0000 0000 0000 0000 0000 0111 0000 SFR addr. 95H Bit functions and addresses MSB LSB Reset value Hex 00 Binary 0000 0000
Product data sheet Rev. 5 -- 10 January 2011 23 of 94
P89LPC9331_9341_9351_9361 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved.
NXP Semiconductors
DPTR DPH DPL FMADRH FMADRL FMCON
8-bit microcontroller with accelerated two-clock 80C51 core
P89LPC9331/9341/9351/9361
FMCMD.7 FMCMD.6 FMCMD.5 FMCMD.4 FMCMD.3 FMCMD.2 FMCMD.1 FMCMD.0 00 00 0000 0000 0000 0000
Bit address I2CON* D8H
I2SCLL
DCH
00
0000 0000
I2STAT
D9H
STA.4
STA.3
STA.2
STA.1
STA.0
0
0
0
F8
1111 1000
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Table 6. Special function registers - P89LPC9351/9361 * indicates SFRs that are bit addressable. Name ICRAH ICRAL ICRBH ICRBL Description Input capture A register high Input capture A register low Input capture B register high Input capture B register low Interrupt enable 0 Interrupt enable 1 Interrupt priority 0 Interrupt priority 0 high Interrupt priority 1 Interrupt priority 1 high Keypad control register Keypad interrupt mask register Keypad pattern register Output compare A register high Output compare A register low Output compare B register high SFR addr. ABH AAH AFH AEH AF EA EF EADEE BF FF PADEE PAEEH AE EWDRT EE EST BE PWDRT PWDRTH FE PST PSTH AD EBO ED BD PBO PBOH FD AC ES/ESR EC ECCU BC PS/PSR PSH/ PSRH FC PCCU PCCUH AB ET1 EB ESPI BB PT1 PT1H FB PSPI PSPIH AA EX1 EA EC BA PX1 PX1H FA PC PCH A9 ET0 E9 EKBI B9 PT0 PT0H F9 PKBI PKBIH PATN _SEL A8 EX0 E8 EI2C B8 PX0 PX0H F8 PI2C PI2CH KBIF 00[1] 00[1] 00[1] 00 FF 00 00 00 00x0 0000 00x0 0000 xxxx xx00 0000 0000 1111 1111 0000 0000 0000 0000 0000 0000 00[1] 00[1] x000 0000 x000 0000 00[1] 00x0 0000 00 0000 0000 Bit functions and addresses MSB LSB Reset value Hex 00 00 00 00 Binary 0000 0000 0000 0000 0000 0000 0000 0000
Product data sheet Rev. 5 -- 10 January 2011 24 of 94
P89LPC9331_9341_9351_9361 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved.
NXP Semiconductors
Bit address IEN0* IEN1* IP0* IP0H A8H E8H B8H B7H Bit address Bit address
8-bit microcontroller with accelerated two-clock 80C51 core
P89LPC9331/9341/9351/9361
Bit address IP1* IP1H KBCON KBMASK KBPATN OCRAH OCRAL OCRBH F8H F7H 94H 86H 93H EFH EEH FBH
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Table 6. Special function registers - P89LPC9351/9361 * indicates SFRs that are bit addressable. Name OCRBL OCRCH OCRCL OCRDH OCRDL
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Product data sheet Rev. 5 -- 10 January 2011 25 of 94
P89LPC9331_9341_9351_9361
NXP Semiconductors
Description Output compare B register low Output compare C register high Output compare C register low Output compare D register high Output compare D register low Port 0
SFR addr. FAH FDH FCH FFH FEH
Bit functions and addresses MSB LSB
Reset value Hex 00 00 00 00 00 Binary 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
Bit address P0* 80H Bit address P1* P2* P3* P0M1 P0M2 P1M1 P1M2 P2M1 P2M2 Port 1 Port 2 Port 3 Port 0 output mode 1 Port 0 output mode 2 Port 1 output mode 1 Port 1 output mode 2 Port 2 output mode 1 Port 2 output mode 2 90H Bit address A0H Bit address B0H 84H 85H 91H 92H A4H A5H
87 T1/KB7 97 OCC A7 ICA B7 (P0M1.7) (P0M2.7) (P1M1.7) (P1M2.7) (P2M1.7) (P2M2.7)
86 CMP1 /KB6 96 OCB A6 OCA B6 (P0M1.6) (P0M2.6) (P1M1.6) (P1M2.6) (P2M1.6) (P2M2.6)
85 CMPREF /KB5 95 RST A5 SPICLK B5 (P0M1.5) (P0M2.5) (P2M1.5) (P2M2.5)
84 CIN1A /KB4 94 INT1 A4 SS B4 (P0M1.4) (P0M2.4) (P1M1.4) (P1M2.4) (P2M1.4) (P2M2.4)
83 CIN1B /KB3 93 INT0/SDA A3 MISO B3 (P0M1.3) (P0M2.3) (P1M1.3) (P1M2.3) (P2M1.3) (P2M2.3)
82 CIN2A /KB2 92 T0/SCL A2 MOSI B2 (P0M1.2) (P0M2.2) (P1M1.2) (P1M2.2) (P2M1.2) (P2M2.2)
81 CIN2B /KB1 91 RXD A1 OCD B1 XTAL1 (P0M1.1) (P0M2.1) (P1M1.1) (P1M2.1) (P2M1.1) (P2M2.1)
80 CMP2 /KB0 90 TXD A0 ICB B0 XTAL2 (P0M1.0) (P0M2.0) (P1M1.0) (P1M2.0) (P2M1.0) (P2M2.0)
[1] [1] [1] [1]
8-bit microcontroller with accelerated two-clock 80C51 core
P89LPC9331/9341/9351/9361
FF[1] 00[1] D3[1] 00[1] FF[1] 00[1]
1111 1111 0000 0000 11x1 xx11 00x0 xx00 1111 1111 0000 0000
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Table 6. Special function registers - P89LPC9351/9361 * indicates SFRs that are bit addressable. Name P3M1 P3M2 PCON PCONA Description Port 3 output mode 1 Port 3 output mode 2 Power control register Power control register A Program status word Port 0 digital input disable Reset source register RTC control RTC register high RTC register low Serial port address register Serial port address enable Serial Port data buffer register Serial port control Serial port extended status register Stack pointer SPI control register SFR addr. B1H B2H 87H B5H Bit address
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Product data sheet Rev. 5 -- 10 January 2011 26 of 94
P89LPC9331_9341_9351_9361
NXP Semiconductors
Bit functions and addresses MSB SMOD1 RTCPD D7 CY RTCF SMOD0 DEEPD D6 AC BOIF RTCS1 VCPD D5 F0 PT0AD.5 BOF RTCS0 BOI ADPD D4 RS1 PT0AD.4 POF GF1 I2PD D3 RS0 PT0AD.3 R_BK GF0 SPPD D2 OV PT0AD.2 R_WD (P3M1.1) (P3M2.1) PMOD1 SPD D1 F1 PT0AD.1 R_SF ERTC LSB (P3M1.0) (P3M2.0) PMOD0 CCUPD D0 P R_EX RTCEN
Reset value Hex 03[1] 00[1] 00 00[1] Binary xxxx xx11 xxxx xx00 0000 0000 0000 0000
PSW* PT0AD RSTSRC RTCCON RTCH RTCL SADDR SADEN SBUF
D0H F6H DFH D1H D2H D3H A9H B9H 99H
00 00
[3]
0000 0000 xx00 000x
8-bit microcontroller with accelerated two-clock 80C51 core
P89LPC9331/9341/9351/9361
60[1][6] 011x xx00 00[6] 00[6] 00 00 xx 0000 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx
Bit address SCON* SSTAT 98H BAH
9F SM0/FE DBMOD
9E SM1 INTLO
9D SM2 CIDIS
9C REN DBISEL
9B TB8 FE
9A RB8 BR
99 TI OE
98 RI STINT 00 00 0000 0000 0000 0000
SP SPCTL
81H E2H SSIG SPEN DORD MSTR CPOL CPHA SPR1 SPR0
07 04
0000 0111 0000 0100
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Table 6. Special function registers - P89LPC9351/9361 * indicates SFRs that are bit addressable. Name SPSTAT SPDAT TAMOD Description SPI status register SPI data register Timer 0 and 1 auxiliary mode Timer 0 and 1 control CCU control register 0 CCU control register 1 Timer 0 high Timer 1 high CCU timer high CCU interrupt control register CCU interrupt flag register CCU interrupt status encode register Timer 0 low Timer 1 low CCU timer low Timer 0 and 1 mode CCU reload register high CCU reload register low Prescaler control register high SFR addr. E1H E3H 8FH Bit address TCON* TCR20* TCR21 TH0 TH1 TH2 TICR2 TIFR2 TISE2 88H C8H F9H 8CH 8DH CDH C9H E9H DEH TOIE2 TOIF2 TOCIE2D TOCF2D TOCIE2C TOCF2C TOCIE2B TOCF2B TOCIE2A TOCF2A ENCINT.2 TICIE2B TICF2B ENCINT.1 TICIE2A TICF2A 8F TF1 PLEEN TCOU2 8E TR1 HLTRN 8D TF0 HLTEN T1M2 8C TR0 ALTCD 8B IE1 ALTAB PLLDV.3 8A IT1 TDIR2 PLLDV.2 89 IE0 TMOD21 PLLDV.1 T0M2 88 IT0 TMOD20 PLLDV.0 00 00 00 00 00 00 00 00 0000 0000 0000 0000 0xxx 0000 Bit functions and addresses MSB SPIF WCOL LSB Reset value Hex 00 00 00 Binary 00xx xxxx 0000 0000 xxx0 xxx0
Product data sheet Rev. 5 -- 10 January 2011 27 of 94
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8-bit microcontroller with accelerated two-clock 80C51 core
0000 0000 0000 0000 0000 0000 0000 0x00 0000 0x00 xxxx x000
P89LPC9331/9341/9351/9361
ENCINT.0 00
TL0 TL1 TL2 TMOD TOR2H TOR2L TPCR2H
8AH 8BH CCH 89H CFH CEH CBH T1GATE T1C/T T1M1 T1M0 T0GATE T0C/T T0M1 T0M0
00 00 00 00 00 00 TPCR2H.1 TPCR2H.0 00
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 xxxx xx00
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Table 6. Special function registers - P89LPC9351/9361 * indicates SFRs that are bit addressable. Name TPCR2L TRIM WDCON WDL WFEED1 WFEED2
[1] [2] [3] [4] [5] [6]
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NXP Semiconductors
Description Prescaler control register low Internal oscillator trim register Watchdog control register Watchdog load Watchdog feed 1 Watchdog feed 2
SFR addr. CAH 96H A7H C1H C2H C3H
Bit functions and addresses MSB LSB
Reset value Hex Binary 0000 0000
TPCR2L.7 TPCR2L.6 TPCR2L.5 TPCR2L.4 TPCR2L.3 TPCR2L.2 TPCR2L.1 TPCR2L.0 00 RCCLK PRE2 ENCLK PRE1 TRIM.5 PRE0 TRIM.4 TRIM.3 TRIM.2 WDRUN TRIM.1 WDTOF TRIM.0 WDCLK
[5][6]
[4][6]
FF
1111 1111
All ports are in input only (high-impedance) state after power-up. BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable.
8-bit microcontroller with accelerated two-clock 80C51 core
The RSTSRC register reflects the cause of the P89LPC9351/9361 reset except BOIF bit. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset value is x011 0000. After reset, the value is 1110 01x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset. Other resets will not affect WDTOF. On power-on reset and watchdog reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register. The only reset sources that affect these SFRs are power-on reset and watchdog reset.
P89LPC9331/9341/9351/9361
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Product data sheet Rev. 5 -- 10 January 2011 29 of 94
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Table 7. Name BODCFG
Extended special function registers - P89LPC9351/9361[1] Description BOD configuration register CLOCK Control register PGA1 control register PGA1 control register B SFR addr. FFC8H Bit functions and addresses MSB BOICFG1 LSB BOICFG0 Reset value Hex Binary
[2]
CLKCON
FFDEH
CLKOK
-
-
XTALWD
CLKDBL
FOSC2
FOSC1
FOSC0
[3]
1000 xxxx
PGACON1 PGACON1B
FFE1H FFE4H FFE3H FFE2H FFCAH FFCEH
ENPGA1 -
PGASEL1 PGASEL1 1 0 -
PGATRIM 1 -
8XTRIM3 2XTRIM3 TSEL1 8XTRIM3 2XTRIM3
8XTRIM2 2XTRIM2 TSEL0 8XTRIM2 2XTRIM2
PGAG11 8XTRIM1 2XTRIM1 PGAG01 8XTRIM1 2XTRIM1
PGAG10
00
0000 0000 0000 0000
PGAENO 00 FF1 8XTRIM0 2XTRIM0 PGAG00
[4]
PGA1TRIM8X16X PGA1 trim register PGA1TRIM2X4X PGACON0 PGACON0B PGA1 trim register PGA0 control register PGA0 control register B
16XTRIM3 16XTRIM2 16XTRIM1 16XTRIM0 4XTRIM3 ENPGA0 4XTRIM2 4XTRIM1 4XTRIM0 PGATRIM 0 -
[4]
8-bit microcontroller with accelerated two-clock 80C51 core
PGASEL0 PGASEL0 1 0 -
00
0000 0000 0000 0000
P89LPC9331/9341/9351/9361
PGAENO 00 FF0 8XTRIM0 2XTRIM0
[4]
PGA0TRIM8X16X PGA0 trim register PGA0TRIM2X4X RTCDATH PGA0 trim register Real-time clock data register high Real-time clock data register low
FFCDH 16XTRIM3 16XTRIM2 16XTRIM1 16XTRIM0 FFCCH FFBFH 4XTRIM3 4XTRIM2 4XTRIM1 4XTRIM0
[4]
00
0000 0000
RTCDATL
FFBEH
00
0000 0000
[1] [2] [3] [4]
Extended SFRs are physically located on-chip but logically located in external data memory address space (XDATA). The MOVX A,@DPTR and MOVX @DPTR,A instructions are used to access these extended SFRs. The BOICFG1/0 will be copied from UCFG1.5 and UCFG1.3 when power-on reset. CLKCON register reset value comes from UCFG1 and UCFG2. The reset value of CLKCON.2 to CLKCON.0 come from UCFG1.2 to UCFG1.0 and reset value of CLKDBL bit comes from UCFG2.7. On power-on reset and watchdog reset, the PGAxTRIM8X16X and PGAxTRIM2X4X registers are initialized with a factory preprogrammed value. Other resets will not cause initialization.
NXP Semiconductors
P89LPC9331/9341/9351/9361
8-bit microcontroller with accelerated two-clock 80C51 core
7.2 Enhanced CPU
The P89LPC9331/9341/9351/9361 uses an enhanced 80C51 CPU which runs at six times the speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and most instructions execute in one or two machine cycles.
7.3 Clocks
7.3.1 Clock definitions
The P89LPC9331/9341/9351/9361 device has several internal clocks as defined below: OSCCLK -- Input to the DIVM clock divider. OSCCLK is selected from one of four clock sources (see Figure 7) and can also be optionally divided to a slower frequency (see Section 7.11 "CCLK modification: DIVM register"). Remark: fosc is defined as the OSCCLK frequency. CCLK -- CPU clock; output of the clock divider. There are two CCLK cycles per machine cycle, and most instructions are executed in one to two machine cycles (two or four CCLK cycles). RCCLK -- The internal 7.373 MHz RC oscillator output. The clock doubler option, when enabled, provides an output frequency of 14.746 MHz. PCLK -- Clock for the various peripheral devices and is CCLK2.
7.3.2 CPU clock (OSCCLK)
The P89LPC9331/9341/9351/9361 provides several user-selectable oscillator options in generating the CPU clock. This allows optimization for a range of needs from high precision to lowest possible cost. These options are configured when the flash is programmed and include an on-chip watchdog oscillator, an on-chip RC oscillator, an oscillator using an external crystal, or an external clock source.
7.4 Crystal oscillator option
The crystal oscillator option can be optimized for low, medium, or high frequency crystals covering a range from 20 kHz to 18 MHz. It can be the clock source of OSCCLK, and RTC. Low speed oscillator option can be the clock source of WDT.
7.4.1 Low speed oscillator option
This option supports an external crystal in the range of 20 kHz to 100 kHz. Ceramic resonators are also supported in this configuration.
7.4.2 Medium speed oscillator option
This option supports an external crystal in the range of 100 kHz to 4 MHz. Ceramic resonators are also supported in this configuration.
7.4.3 High speed oscillator option
This option supports an external crystal in the range of 4 MHz to 18 MHz. Ceramic resonators are also supported in this configuration.
P89LPC9331_9341_9351_9361
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P89LPC9331/9341/9351/9361
8-bit microcontroller with accelerated two-clock 80C51 core
7.5 Clock output
The P89LPC9331/9341/9351/9361 supports a user-selectable clock output function on the XTAL2/CLKOUT pin when crystal oscillator is not being used. This condition occurs if another clock source has been selected (on-chip RC oscillator, watchdog oscillator, external clock input on XTAL1) and if the RTC and WDT are not using the crystal oscillator as their clock source. This allows external devices to synchronize to the P89LPC9331/9341/9351/9361. This output is enabled by the ENCLK bit in the TRIM register. The frequency of this clock output is 12 that of the CCLK. If the clock output is not needed in Idle mode, it may be turned off prior to entering Idle, saving additional power.
7.6 On-chip RC oscillator option
The P89LPC9331/9341/9351/9361 has a 6-bit TRIM register that can be used to tune the frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory preprogrammed value to adjust the oscillator frequency to 7.373 MHz 1 % at room temperature. End-user applications can write to the TRIM register to adjust the on-chip RC oscillator to other frequencies. When the clock doubler option is enabled (UCFG2.7 = 1), the output frequency is 14.746 MHz. If CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to logic 1 to reduce power consumption. On reset, CLKLP is logic 0 allowing highest performance access. This bit can then be set in software if CCLK is running at 8 MHz or slower. When clock doubler option is enabled, BOE1 bit (UCFG1.5) and BOE0 bit (UCFG1.3) are required to hold the device in reset at power-up until VDD has reached its specified level.
7.7 Watchdog oscillator option
The watchdog has a separate oscillator which has a frequency of 400 kHz, calibrated to 5 % at room temperature. This oscillator can be used to save power when a high clock frequency is not needed.
7.8 External clock input option
In this configuration, the processor clock is derived from an external source driving the P3.1/XTAL1 pin. The rate may be from 0 Hz up to 18 MHz. The P3.0/XTAL2 pin may be used as a standard port pin or a clock output. When using an oscillator frequency above 12 MHz, BOE1 bit (UCFG1.5) and BOE0 bit (UCFG1.3) are required to hold the device in reset at power-up until VDD has reached its specified level.
7.9 Clock source switching on the fly
P89LPC9331/9341/9351/9361 can implement clock switching on any sources of watchdog oscillator, 7 MHz/14 MHz internal RC oscillator, crystal oscillator and external clock input during code is running. CLKOK bit in CLKCON register is used to indicate the clock switch status. CLKOK is cleared when starting clock source switch and set when completed. Notice that when CLKOK is `0', writing to CLKCON register is not allowed.
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P89LPC9331/9341/9351/9361
8-bit microcontroller with accelerated two-clock 80C51 core
XTAL1 XTAL2
HIGH FREQUENCY MEDIUM FREQUENCY LOW FREQUENCY
RTC
ADC1
ADC0
OSCCLK RC OSCILLATOR WITH CLOCK DOUBLER RCCLK
DIVM
CCLK /2 PCLK
CPU
(7.3728 MHz/14.7456 MHz 1 %) WATCHDOG OSCILLATOR (400 kHz 5 %) TIMER 0 AND TIMER 1 PCLK
WDT
32 x PLL CCU
I2C-BUS
SPI
UART
(P89LPC9351/9361)
002aad559
Fig 7.
Block diagram of oscillator control
7.10 CCLK wake-up delay
The P89LPC9331/9341/9351/9361 has an internal wake-up timer that delays the clock until it stabilizes depending on the clock source used. If the clock source is any of the three crystal selections (low, medium and high frequencies) the delay is 1024 OSCCLK cycles plus 60 s to 100 s. If the clock source is the internal RC oscillator, the delay is 200 s to 300 s. If the clock source is watchdog oscillator or external clock, the delay is 32 OSCCLK cycles.
7.11 CCLK modification: DIVM register
The OSCCLK frequency can be divided down up to 510 times by configuring a dividing register, DIVM, to generate CCLK. This feature makes it possible to temporarily run the CPU at a lower rate, reducing power consumption. By dividing the clock, the CPU can retain the ability to respond to events that would not exit Idle mode by executing its normal program at a lower rate. This can also allow bypassing the oscillator start-up time in cases where Power-down mode would otherwise be used. The value of DIVM may be changed by the program at any time without interrupting code execution.
7.12 Low power select
The P89LPC9331/9341/9351/9361 is designed to run at 18 MHz (CCLK) maximum. However, if CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to logic 1 to lower the power consumption further. On any reset, CLKLP is logic 0 allowing highest performance access. This bit can then be set in software if CCLK is running at 8 MHz or slower.
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P89LPC9331/9341/9351/9361
8-bit microcontroller with accelerated two-clock 80C51 core
7.13 Memory organization
The various P89LPC9331/9341/9351/9361 memory spaces are as follows:
* DATA
128 bytes of internal data memory space (00H:7FH) accessed via direct or indirect addressing, using instructions other than MOVX and MOVC. All or part of the Stack may be in this area.
* IDATA
Indirect Data. 256 bytes of internal data memory space (00H:FFH) accessed via indirect addressing using instructions other than MOVX and MOVC. All or part of the Stack may be in this area. This area includes the DATA area and the 128 bytes immediately above it.
* SFR
Special Function Registers. Selected CPU registers and peripheral control and status registers, accessible only via direct addressing.
* XDATA (P89LPC9351/9361)
`External' Data or Auxiliary RAM. Duplicates the classic 80C51 64 kB memory space addressed via the MOVX instruction using the DPTR, R0, or R1. All or part of this space could be implemented on-chip. The P89LPC9351/9361 has 512 bytes of on-chip XDATA memory, plus extended SFRs located in XDATA.
* CODE
64 kB of Code memory space, accessed as part of program execution and via the MOVC instruction. The P89LPC9331/9341/9351/9361 has 4 kB/8 kB/16 kB of on-chip Code memory. The P89LPC9351/9361 also has 512 bytes of on-chip data EEPROM that is accessed via SFRs (see Section 7.14).
7.14 Data RAM arrangement
The 768 bytes of on-chip RAM are organized as shown in Table 8.
Table 8. Type DATA IDATA XDATA On-chip data memory usages Data RAM Memory that can be addressed directly and indirectly Memory that can be addressed indirectly Auxiliary (External Data) on-chip memory that is accessed using the MOVX instructions (P89LPC9351/9361) Size (bytes) 128 256 512
7.15 Interrupts
The P89LPC9331/9341/9351/9361 uses a four priority level interrupt structure. This allows great flexibility in controlling the handling of the many interrupt sources. The P89LPC9331/9341/9351/9361 supports 15 interrupt sources: external interrupts 0 and 1, timers 0 and 1, serial port TX, serial port RX, combined serial port RX/TX, brownout detect, watchdog/RTC, I2C-bus, keyboard, comparators 1 and 2, SPI, CCU, data EEPROM write/ADC completion.
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P89LPC9331/9341/9351/9361
8-bit microcontroller with accelerated two-clock 80C51 core
Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a global disable bit, EA, which disables all interrupts. Each interrupt source can be individually programmed to one of four priority levels by setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1 and IP1H. An interrupt service routine in progress can be interrupted by a higher priority interrupt, but not by another interrupt of the same or lower priority. The highest priority interrupt service cannot be interrupted by any other interrupt source. If two requests of different priority levels are pending at the start of an instruction, the request of higher priority level is serviced. If requests of the same priority level are pending at the start of an instruction, an internal polling sequence determines which request is serviced. This is called the arbitration ranking. Note that the arbitration ranking is only used to resolve pending requests of the same priority level.
7.15.1 External interrupt inputs
The P89LPC9331/9341/9351/9361 has two external interrupt inputs as well as the Keypad Interrupt function. The two interrupt inputs are identical to those present on the standard 80C51 microcontrollers. These external interrupts can be programmed to be level-triggered or edge-triggered by setting or clearing bit IT1 or IT0 in Register TCON. In edge-triggered mode, if successive samples of the INTn pin show a HIGH in one cycle and a LOW in the next cycle, the interrupt request flag IEn in TCON is set, causing an interrupt request. If an external interrupt is enabled when the P89LPC9331/9341/9351/9361 is put into Power-down or Idle mode, the interrupt will cause the processor to wake-up and resume operation. Refer to Section 7.18 "Power reduction modes" for details.
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P89LPC9331/9341/9351/9361
8-bit microcontroller with accelerated two-clock 80C51 core
IE0 EX0 IE1 EX1 BOIF EBO RTCF ERTC (RTCCON.1) WDOVF KBIF EKBI EWDRT CMF2 CMF1 EC EA (IE0.7) TF0 ET0 TF1 ET1 TI & RI/RI ES/ESR TI EST SI EI2C SPIF ESPI any CCU interrupt(1) ECCU
EEIF(2) ENADCI0 ADCI0 ENADCI1 ADCI1 ENBI0 BNDI0 ENBI1 BNDI1 EADEE(2) EAD(3)
wake-up (if in power-down)
interrupt to CPU
002aad560
(1) See Section 7.22 "CCU (P89LPC9351/9361)". (2) P89LPC9351/9361 (3) P89LPC9331/9341
Fig 8.
Interrupt sources, interrupt enables, and power-down wake-up sources
P89LPC9331_9341_9351_9361
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P89LPC9331/9341/9351/9361
8-bit microcontroller with accelerated two-clock 80C51 core
7.16 I/O ports
The P89LPC9331/9341/9351/9361 has four I/O ports: Port 0, Port 1, Port 2 and Port 3. Ports 0, 1, and 2 are 8-bit ports, and Port 3 is a 2-bit port. The exact number of I/O pins available depends upon the clock and reset options chosen, as shown in Table 9.
Table 9. Number of I/O pins available Reset option Number of I/O pins (28-pin package) 26 25 25 24 24 23
Clock source
On-chip oscillator or watchdog oscillator External clock input
No external reset (except during power-up) External RST pin supported No external reset (except during power-up) External RST pin supported No external reset (except during power-up) External RST pin supported
Low/medium/high speed oscillator (external crystal or resonator)
7.16.1 Port configurations
All but three I/O port pins on the P89LPC9331/9341/9351/9361 may be configured by software to one of four types on a bit-by-bit basis. These are: quasi-bidirectional (standard 80C51 port outputs), push-pull, open drain, and input-only. Two configuration registers for each port select the output type for each port pin. 1. P1.5 (RST) can only be an input and cannot be configured. 2. P1.2 (SCL/T0) and P1.3 (SDA/INT0) may only be configured to be either input-only or open-drain. 7.16.1.1 Quasi-bidirectional output configuration Quasi-bidirectional output type can be used as both an input and output without the need to reconfigure the port. This is possible because when the port outputs a logic HIGH, it is weakly driven, allowing an external device to pull the pin LOW. When the pin is driven LOW, it is driven strongly and able to sink a fairly large current. These features are somewhat similar to an open-drain output except that there are three pull-up transistors in the quasi-bidirectional output that serve different purposes. The P89LPC9331/9341/9351/9361 is a 3 V device, but the pins are 5 V-tolerant. In quasi-bidirectional mode, if a user applies 5 V on the pin, there will be a current flowing from the pin to VDD, causing extra power consumption. Therefore, applying 5 V in quasi-bidirectional mode is discouraged. A quasi-bidirectional port pin has a Schmitt trigger input that also has a glitch suppression circuit. 7.16.1.2 Open-drain output configuration The open-drain output configuration turns off all pull-ups and only drives the pull-down transistor of the port driver when the port latch contains a logic 0. To be used as a logic output, a port configured in this manner must have an external pull-up, typically a resistor tied to VDD.
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8-bit microcontroller with accelerated two-clock 80C51 core
An open-drain port pin has a Schmitt trigger input that also has a glitch suppression circuit. 7.16.1.3 Input-only configuration The input-only port configuration has no output drivers. It is a Schmitt trigger input that also has a glitch suppression circuit. 7.16.1.4 Push-pull output configuration The push-pull output configuration has the same pull-down structure as both the open-drain and the quasi-bidirectional output modes, but provides a continuous strong pull-up when the port latch contains a logic 1. The push-pull mode may be used when more source current is needed from a port output. A push-pull port pin has a Schmitt triggered input that also has a glitch suppression circuit. The P89LPC9331/9341/9351/9361 device has high current source on eight pins in push-pull mode. See Table 11 "Limiting values".
7.16.2 Port 0 analog functions
The P89LPC9331/9341/9351/9361 incorporates two Analog Comparators. In order to give the best analog function performance and to minimize power consumption, pins that are being used for analog functions must have the digital outputs and digital inputs disabled. Digital outputs are disabled by putting the port output into the Input-Only (high-impedance) mode. Digital inputs on Port 0 may be disabled through the use of the PT0AD register, bits 1:5. On any reset, PT0AD[1:5] defaults to logic 0s to enable digital functions.
7.16.3 Additional port features
After power-up, all pins are in Input-Only mode. Please note that this is different from the LPC76x series of devices.
* After power-up, all I/O pins except P1.5, may be configured by software. * Pin P1.5 is input only. Pins P1.2 and P1.3 are configurable for either input-only or
open-drain. Every output on the P89LPC9331/9341/9351/9361 has been designed to sink typical LED drive current. However, there is a maximum total output current for all ports which must not be exceeded. Please refer to Table 12 "Static characteristics" for detailed specifications. All ports pins that can function as an output have slew rate controlled outputs to limit noise generated by quickly switching output signals. The slew rate is factory-set to approximately 10 ns rise and fall times.
7.17 Power monitoring functions
The P89LPC9331/9341/9351/9361 incorporates power monitoring functions designed to prevent incorrect operation during initial power-up and power loss or reduction during operation. This is accomplished with two hardware functions: Power-on detect and brownout detect.
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7.17.1 Brownout detection
The brownout detect function determines if the power supply voltage drops below a certain level. Enhanced brownout detection has 3 independent functions: BOD reset, BOD interrupt and BOD EEPROM/FLASH. BOD reset is always on except in total Power-down mode. It could not be disabled in software. BOD interrupt may be enabled or disabled in software. BOD EEPROM/FLASH is always on, except in Power-down modes and could not be disabled in software. BOD reset and BOD interrupt, each has four trip voltage levels. BOE1 bit (UCFG1.5) and BOE0 bit (UCFG1.3) are used as trip point configuration bits of BOD reset. BOICFG1 bit and BOICFG0 bit in register BODCFG are used as trip point configuration bits of BOD interrupt. BOD reset voltage should be lower than BOD interrupt trip point. BOD EEPROM/FLASH is used for flash/Data EEPROM programming/erase protection and has only 1 trip voltage of 2.4 V. Please refer to P89LPC9331/9341/9351/9361 User manual for detail configurations. If brownout detection is enabled the brownout condition occurs when VDD falls below the brownout trip voltage and is negated when VDD rises above the brownout trip voltage. For correct activation of brownout detect, the VDD rise and fall times must be observed. Please see Table 12 "Static characteristics" for specifications.
7.17.2 Power-on detection
The Power-on detect has a function similar to the brownout detect, but is designed to work as power comes up initially, before the power supply voltage reaches a level where brownout detect can work. The POF flag in the RSTSRC register is set to indicate an initial power-up condition. The POF flag will remain set until cleared by software.
7.18 Power reduction modes
The P89LPC9331/9341/9351/9361 supports three different power reduction modes. These modes are Idle mode, Power-down mode, and total Power-down mode.
7.18.1 Idle mode
Idle mode leaves peripherals running in order to allow them to activate the processor when an interrupt is generated. Any enabled interrupt source or reset may terminate Idle mode.
7.18.2 Power-down mode
The Power-down mode stops the oscillator in order to minimize power consumption. The P89LPC9331/9341/9351/9361 exits Power-down mode via any reset, or certain interrupts. In Power-down mode, the power supply voltage may be reduced to the data retention supply voltage VDDR. This retains the RAM contents at the point where Power-down mode was entered. SFR contents are not guaranteed after VDD has been lowered to VDDR, therefore it is highly recommended to wake-up the processor via reset in this case. VDD must be raised to within the operating range before the Power-down mode is exited.
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Some chip functions continue to operate and draw power during Power-down mode, increasing the total power used during power-down. These include: Brownout detect, watchdog timer, comparators (note that comparators can be powered down separately), and RTC/system timer. The internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock and the RTC is enabled.
7.18.3 Total Power-down mode
This is the same as Power-down mode except that the brownout detection circuitry and the voltage comparators are also disabled to conserve additional power. The internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock and the RTC is enabled. If the internal RC oscillator is used to clock the RTC during power-down, there will be high power consumption. Please use an external low frequency clock to achieve low power with the RTC running during power-down.
7.19 Reset
The P1.5/RST pin can function as either a LOW-active reset input or as a digital input, P1.5. The Reset Pin Enable (RPE) bit in UCFG1, when set to logic 1, enables the external reset input function on P1.5. When cleared, P1.5 may be used as an input pin. Remark: During a power-up sequence, the RPE selection is overridden and this pin always functions as a reset input. An external circuit connected to this pin should not hold this pin LOW during a power-on sequence as this will keep the device in reset. After power-up this pin will function as defined by the RPE bit. Only a power-up reset will temporarily override the selection defined by RPE bit. Other sources of reset will not override the RPE bit. When this pin functions as a reset input, an internal pull-up resistance is connected (see Table 12 "Static characteristics"). Note: During a power cycle, VDD must fall below VPOR before power is reapplied, in order to ensure a power-on reset (see Table 12 "Static characteristics"). Reset can be triggered from the following sources:
* * * * * *
External reset pin (during power-up or if user configured via UCFG1) Power-on detect Brownout detect Watchdog timer Software reset UART break character detect reset
For every reset source, there is a flag in the Reset Register, RSTSRC. The user can read this register to determine the most recent reset source. These flag bits can be cleared in software by writing a logic 0 to the corresponding bit. More than one flag bit may be set:
* During a power-on reset, both POF and BOF are set but the other flag bits are
cleared.
* A Watchdog reset is similar to a power-on reset, both POF and BOF are set but the
other flag bits are cleared.
* For any other reset, previously set flag bits that have not been cleared will remain set.
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7.19.1 Reset vector
Following reset, the P89LPC9331/9341/9351/9361 will fetch instructions from either address 0000H or the Boot address. The Boot address is formed by using the boot vector as the high byte of the address and the low byte of the address = 00H. The boot address will be used if a UART break reset occurs, or the non-volatile boot status bit (BOOTSTAT.0) = 1, or the device is forced into ISP mode during power-on (see P89LPC9331/9341/9351/9361 User manual). Otherwise, instructions will be fetched from address 0000H.
7.20 Timers/counters 0 and 1
The P89LPC9331/9341/9351/9361 has two general purpose counter/timers which are upward compatible with the standard 80C51 Timer 0 and Timer 1. Both can be configured to operate either as timers or event counters. An option to automatically toggle the T0 and/or T1 pins upon timer overflow has been added. In the `Timer' function, the register is incremented every machine cycle. In the `Counter' function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T0 or T1. In this function, the external input is sampled once during every machine cycle. Timer 0 and Timer 1 have five operating modes (Modes 0, 1, 2, 3 and 6). Modes 0, 1, 2 and 6 are the same for both Timers/Counters. Mode 3 is different.
7.20.1 Mode 0
Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit Counter with a divide-by-32 prescaler. In this mode, the Timer register is configured as a 13-bit register. Mode 0 operation is the same for Timer 0 and Timer 1.
7.20.2 Mode 1
Mode 1 is the same as Mode 0, except that all 16 bits of the timer register are used.
7.20.3 Mode 2
Mode 2 configures the Timer register as an 8-bit Counter with automatic reload. Mode 2 operation is the same for Timer 0 and Timer 1.
7.20.4 Mode 3
When Timer 1 is in Mode 3 it is stopped. Timer 0 in Mode 3 forms two separate 8-bit counters and is provided for applications that require an extra 8-bit timer. When Timer 1 is in Mode 3 it can still be used by the serial port as a baud rate generator.
7.20.5 Mode 6
In this mode, the corresponding timer can be changed to a PWM with a full period of 256 timer clocks.
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7.20.6 Timer overflow toggle output
Timers 0 and 1 can be configured to automatically toggle a port output whenever a timer overflow occurs. The same device pins that are used for the T0 and T1 count inputs are also used for the timer toggle outputs. The port outputs will be a logic 1 prior to the first timer overflow when this mode is turned on.
7.21 RTC/system timer
The P89LPC9331/9341/9351/9361 has a simple RTC that allows a user to continue running an accurate timer while the rest of the device is powered down. The RTC can be a wake-up or an interrupt source. The RTC is a 23-bit down counter comprised of a 7-bit prescaler and a 16-bit loadable down counter. When it reaches all logic 0s, the counter will be reloaded again and the RTCF flag will be set. The clock source for this counter can be either the CPU clock (CCLK) or the XTAL oscillator. Only power-on reset and watchdog reset will reset the RTC and its associated SFRs to the default state. The 16-bit loadable counter portion of the RTC is readable by reading the RTCDATL and RTCDATH registers.
7.22 CCU (P89LPC9351/9361)
This unit features:
* A 16-bit timer with 16-bit reload on overflow. * Selectable clock, with prescaler to divide clock source by any integral number
between 1 and 1024.
* * * *
Four compare/PWM outputs with selectable polarity Symmetrical/asymmetrical PWM selection Two capture inputs with event counter and digital noise rejection filter Seven interrupts with common interrupt vector (one overflow, two capture, four compare)
* Safe 16-bit read/write via shadow registers.
7.22.1 CCU clock
The CCU runs on the CCUCLK, which is either PCLK in basic timer mode, or the output of a PLL. The PLL is designed to use a clock source between 0.5 MHz to 1 MHz that is multiplied by 32 to produce a CCUCLK between 16 MHz and 32 MHz in PWM mode (asymmetrical or symmetrical). The PLL contains a 4-bit divider to help divide PCLK into a frequency between 0.5 MHz and 1 MHz.
7.22.2 CCUCLK prescaling
This CCUCLK can further be divided down by a prescaler. The prescaler is implemented as a 10-bit free-running counter with programmable reload at overflow.
7.22.3 Basic timer operation
The timer is a free-running up/down counter with a direction control bit. If the timer counting direction is changed while the counter is running, the count sequence will be reversed. The timer can be written or read at any time.
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When a reload occurs, the CCU Timer Overflow Interrupt Flag will be set, and an interrupt generated if enabled. The 16-bit CCU timer may also be used as an 8-bit up/down timer.
7.22.4 Output compare
There are four output compare channels: A, B, C and D. Each output compare channel needs to be enabled in order to operate and the user will have to set the associated I/O pin to the desired output mode to connect the pin. When the contents of the timer matches that of a capture compare control register, the Timer Output Compare Interrupt Flag (TOCFx) becomes set. An interrupt will occur if enabled.
7.22.5 Input capture
Input capture is always enabled. Each time a capture event occurs on one of the two input capture pins, the contents of the timer is transferred to the corresponding 16-bit input capture register. The capture event can be programmed to be either rising or falling edge triggered. A simple noise filter can be enabled on the input capture by enabling the Input Capture Noise Filter bit. If set, the capture logic needs to see four consecutive samples of the same value in order to recognize an edge as a capture event. An event counter can be set to delay a capture by a number of capture events.
7.22.6 PWM operation
PWM operation has two main modes, symmetrical and asymmetrical. In asymmetrical PWM operation the CCU timer operates in down-counting mode regardless of the direction control bit. In symmetrical mode, the timer counts up/down alternately. The main difference from basic timer operation is the operation of the compare module, which in PWM mode is used for PWM waveform generation. As with basic timer operation, when the PWM (compare) pins are connected to the compare logic, their logic state remains unchanged. However, since bit FCO is used to hold the halt value, only a compare event can change the state of the pin.
TOR2
compare value timer value 0x0000
non-inverted
inverted
002aaa893
Fig 9.
Asymmetrical PWM, down-counting
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TOR2
compare value timer value 0 non-inverted
inverted
002aaa894
Fig 10. Symmetrical PWM
7.22.7 Alternating output mode
In asymmetrical mode, the user can set up PWM channels A/B and C/D as alternating pairs for bridge drive control. In this mode the output of these PWM channels are alternately gated on every counter cycle.
TOR2 COMPARE VALUE A (or C) COMPARE VALUE B (or D) TIMER VALUE 0
PWM OUTPUT (OCA or OCC)
PWM OUTPUT (OCB or OCD)
002aaa895
Fig 11. Alternate output mode
7.22.8 PLL operation
The PWM module features a Phase Locked Loop that can be used to generate a CCUCLK frequency between 16 MHz and 32 MHz. At this frequency the PWM module provides ultrasonic PWM frequency with 10-bit resolution provided that the crystal frequency is 1 MHz or higher. The PLL is fed an input signal from 0.5 MHz to 1 MHz and generates an output signal of 32 times the input frequency. This signal is used to clock the timer. The user will have to set a divider that scales PCLK by a factor from 1 to 16. This divider is found in the SFR register TCR21. The PLL frequency can be expressed as shown in Equation 1: PCLK PLL frequency = ----------------(N + 1) Where: N is the value of PLLDV3:0.
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Since N ranges from 0 to 15, the CCLK frequency can be in the range of PCLK to PCLK/16.
7.22.9 CCU interrupts
There are seven interrupt sources on the CCU which share a common interrupt vector.
EA (IEN0.7) ECCU (IEN1.4) TOIE2 (TICR2.7) TOIF2 (TIFR2.7) TICIE2A (TICR2.0) TICF2A (TIFR2.0) TICIE2B (TICR2.1) TICF2B (TIFR2.1) TOCIE2A (TICR2.3) TOCF2A (TIFR2.3) TOCIE2B (TICR2.4) TOCF2B (TIFR2.4) TOCIE2C (TICR2.5) TOCF2C (TIFR2.5) TOCIE2D (TICR2.6) TOCF2D (TIFR2.6) interrupt to CPU
other interrupt sources
ENCINT.0 PRIORITY ENCODER ENCINT.1 ENCINT.2
002aaa896
Fig 12. Capture/compare unit interrupts
7.23 UART
The P89LPC9331/9341/9351/9361 has an enhanced UART that is compatible with the conventional 80C51 UART except that Timer 2 overflow cannot be used as a baud rate source. The P89LPC9331/9341/9351/9361 does include an independent baud rate generator. The baud rate can be selected from the oscillator (divided by a constant), Timer 1 overflow, or the independent baud rate generator. In addition to the baud rate generation, enhancements over the standard 80C51 UART include Framing Error detection, automatic address recognition, selectable double buffering and several interrupt options. The UART can be operated in four modes: shift register, 8-bit UART, 9-bit UART, and CPU clock/32 or CPU clock/16.
7.23.1 Mode 0
Serial data enters and exits through RXD. TXD outputs the shift clock. 8 bits are transmitted or received, LSB first. The baud rate is fixed at 116 of the CPU clock frequency.
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7.23.2 Mode 1
10 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0), 8 data bits (LSB first), and a stop bit (logic 1). When data is received, the stop bit is stored in RB8 in special function register SCON. The baud rate is variable and is determined by the Timer 1 overflow rate or the baud rate generator (described in Section 7.23.5 "Baud rate generator and selection").
7.23.3 Mode 2
11 bits are transmitted (through TXD) or received (through RXD): start bit (logic 0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (logic 1). When data is transmitted, the 9th data bit (TB8 in SCON) can be assigned the value of logic 0 or logic 1. Or, for example, the parity bit (P, in the PSW) could be moved into TB8. When data is received, the 9th data bit goes into RB8 in special function register SCON, while the stop bit is not saved. The baud rate is programmable to either 116 or 132 of the CPU clock frequency, as determined by the SMOD1 bit in PCON.
7.23.4 Mode 3
11 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (logic 1). In fact, Mode 3 is the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable and is determined by the Timer 1 overflow rate or the baud rate generator (described in Section 7.23.5 "Baud rate generator and selection").
7.23.5 Baud rate generator and selection
The P89LPC9331/9341/9351/9361 enhanced UART has an independent baud rate generator. The baud rate is determined by a baud-rate preprogrammed into the BRGR1 and BRGR0 SFRs which together form a 16-bit baud rate divisor value that works in a similar manner as Timer 1 but is much more accurate. If the baud rate generator is used, Timer 1 can be used for other timing functions. The UART can use either Timer 1 or the baud rate generator output (see Figure 13). Note that Timer T1 is further divided by 2 if the SMOD1 bit (PCON.7) is cleared. The independent baud rate generators use OSCCLK.
timer 1 overflow (PCLK-based) /2
SMOD1 = 1
SBRGS = 0 baud rate modes 1 and 3
SMOD1 = 0 baud rate generator (CCLK-based)
SBRGS = 1
002aaa897
Fig 13. Baud rate sources for UART (Modes 1, 3)
7.23.6 Framing error
Framing error is reported in the status register (SSTAT). In addition, if SMOD0 (PCON.6) is logic 1, framing errors can be made available in SCON.7 respectively. If SMOD0 is logic 0, SCON.7 is SM0. It is recommended that SM0 and SM1 (SCON.7:6) are set up when SMOD0 is logic 0.
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7.23.7 Break detect
Break detect is reported in the status register (SSTAT). A break is detected when 11 consecutive bits are sensed LOW. The break detect can be used to reset the device and force the device into ISP mode.
7.23.8 Double buffering
The UART has a transmit double buffer that allows buffering of the next character to be written to SnBUF while the first character is being transmitted. Double buffering allows transmission of a string of characters with only one stop bit between any two characters, as long as the next character is written between the start bit and the stop bit of the previous character. Double buffering can be disabled. If disabled (DBMOD, i.e., SSTAT.7 = 0), the UART is compatible with the conventional 80C51 UART. If enabled, the UART allows writing to SBUF while the previous data is being shifted out. Double buffering is only allowed in Modes 1, 2 and 3. When operated in Mode 0, double buffering must be disabled (DBMOD = 0).
7.23.9 Transmit interrupts with double buffering enabled (modes 1, 2 and 3)
Unlike the conventional UART, in double buffering mode, the TI interrupt is generated when the double buffer is ready to receive new data.
7.23.10 The 9th bit (bit 8) in double buffering (modes 1, 2 and 3)
If double buffering is disabled TB8 can be written before or after SBUF is written, as long as TB8 is updated some time before that bit is shifted out. TB8 must not be changed until the bit is shifted out, as indicated by the TI interrupt. If double buffering is enabled, TB must be updated before SBUF is written, as TB8 will be double-buffered together with SBUF data.
7.24 I2C-bus serial interface
The I2C-bus uses two wires (SDA and SCL) to transfer information between devices connected to the bus, and it has the following features:
* Bidirectional data transfer between masters and slaves * Multi master bus (no central master) * Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
* Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus
* Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer
* The I2C-bus may be used for test and diagnostic purposes.
A typical I2C-bus configuration is shown in Figure 14. The P89LPC9331/9341/9351/9361 device provides a byte-oriented I2C-bus interface that supports data transfers up to 400 kHz.
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RP
RP
SDA I2C-bus SCL P1.3/SDA P1.2/SCL
P89LPC9331/9341/ 9351/9361
OTHER DEVICE WITH I2C-BUS INTERFACE
OTHER DEVICE WITH I2C-BUS INTERFACE
002aad731
Fig 14. I2C-bus configuration
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8
ADDRESS REGISTER P1.3
I2ADR
COMPARATOR INPUT FILTER P1.3/SDA OUTPUT STAGE SHIFT REGISTER ACK I2DAT 8
CCLK TIMING AND CONTROL LOGIC interrupt
INPUT FILTER P1.2/SCL OUTPUT STAGE timer 1 overflow P1.2 I2CON I2SCLH I2SCLL
SERIAL CLOCK GENERATOR
CONTROL REGISTERS AND SCL DUTY CYCLE REGISTERS 8
status bus
STATUS DECODER
I2STAT
STATUS REGISTER
8
002aaa899
Fig 15. I2C-bus serial interface block diagram
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INTERNAL BUS
BIT COUNTER / ARBITRATION AND SYNC LOGIC
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7.25 SPI
The P89LPC9331/9341/9351/9361 provides another high-speed serial communication interface: the SPI interface. SPI is a full-duplex, high-speed, synchronous communication bus with two operation modes: Master mode and Slave mode. Up to 3 Mbit/s can be supported in either Master mode or Slave mode. It has a Transfer Completion Flag and Write Collision Flag Protection.
S M CPU clock 8-BIT SHIFT REGISTER DIVIDER BY 4, 16, 64, 128 READ DATA BUFFER M S PIN CONTROL LOGIC
MISO P2.3 MOSI P2.2 SPICLK P2.5 SS P2.4 SPEN
002aaa900
(c) NXP B.V. 2011. All rights reserved.
SPI clock (master) SELECT SPR1 SPR0
clock CLOCK LOGIC S M MSTR DORD MSTR CPHA SPEN CPOL SPR1 SPI CONTROL REGISTER internal data bus
SPI CONTROL WCOL SPIF
MSTR SPEN SPR0 SSIG SPI interrupt request
SPI STATUS REGISTER
Fig 16. SPI block diagram
The SPI interface has four pins: SPICLK, MOSI, MISO and SS:
* SPICLK, MOSI and MISO are typically tied together between two or more SPI
devices. Data flows from master to slave on MOSI (Master Out Slave In) pin and flows from slave to master on MISO (Master In Slave Out) pin. The SPICLK signal is output in the Master mode and is input in the Slave mode. If the SPI system is disabled, i.e., SPEN (SPCTL.6) = 0 (reset value), these pins are configured for port functions.
* SS is the optional slave select pin. In a typical configuration, an SPI master asserts
one of its port pins to select one SPI device as the current slave. An SPI slave device uses its SS pin to determine whether it is selected. Typical connections are shown in Figure 17 through Figure 19.
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7.25.1 Typical SPI configurations
master MISO 8-BIT SHIFT REGISTER MOSI MISO MOSI
slave
8-BIT SHIFT REGISTER
SPICLK SPI CLOCK GENERATOR PORT
SPICLK SS
002aaa901
Fig 17. SPI single master single slave configuration
master MISO 8-BIT SHIFT REGISTER MOSI MISO MOSI
slave
8-BIT SHIFT REGISTER
SPICLK SPI CLOCK GENERATOR SS
SPICLK SS SPI CLOCK GENERATOR
002aaa902
Fig 18. SPI dual device configuration, where either can be a master or a slave
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master MISO 8-BIT SHIFT REGISTER MOSI MISO MOSI
slave
8-BIT SHIFT REGISTER
SPICLK SPI CLOCK GENERATOR port
SPICLK SS
slave MISO MOSI 8-BIT SHIFT REGISTER
SPICLK port SS
002aaa903
Fig 19. SPI single master multiple slaves configuration
7.26 Analog comparators
Two analog comparators are provided on the P89LPC9331/9341/9351/9361. Input and output options allow use of the comparators in a number of different configurations. Comparator operation is such that the output is a logical one (which may be read in a register and/or routed to a pin) when the positive input (one of two selectable inputs) is greater than the negative input (selectable from a pin or an internal reference voltage). Otherwise the output is a zero. Each comparator may be configured to cause an interrupt when the output value changes. In P89LPC9351/9361, the positive inputs of comparators could be amplified by Programmable Gain Amplifier 1 (PGA1) module. The PGA1 can supply gain factors of 2x, 4x, 8x, or 16x, eliminating the need for external op-amps in the end application. The overall connections to both comparators are shown in Figure 20 and Figure 21. The comparators function to VDD = 2.4 V. When each comparator is first enabled, the comparator output and interrupt flag are not guaranteed to be stable for 10 s. The corresponding comparator interrupt should not be enabled during that time, and the comparator interrupt flag must be cleared before the interrupt is enabled in order to prevent an immediate interrupt service. When a comparator is disabled the comparator's output, COn, goes HIGH. If the comparator output was LOW and then is disabled, the resulting transition of the comparator output from a LOW to HIGH state will set the comparator flag, CMFn. This will cause an interrupt if the comparator interrupt is enabled. The user should therefore disable the comparator interrupt prior to disabling the comparator. Additionally, the user should clear the comparator flag, CMFn, after disabling the comparator.
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CP1 (P0.4) CIN1A (P0.3) CIN1B (P0.5) CMPREF Vref(bg) CN1 comparator 1 CO1
change detect
OE1
CMP1 (P0.6)
CMF1
interrupt
change detect
CP2 CMF2 (P0.2) CIN2A (P0.1) CIN2B CMP2 (P0.0) CO2 OE2 CN2 comparator 2
EC
002aae483
Fig 20. Comparator input and output connections (P89LPC9331/9341)
CP1 (P0.4) CIN1A (P0.3) CIN1B PGA1 (P0.2) CIN2A (P0.1) CIN2B (P0.5) CMPREF Vref(bg) CN1 comparator 1 CO1
change detect
OE1
CMP1 (P0.6)
CMF1
interrupt
change detect
CP2 CMF2 comparator 2 CMP2 (P0.0) CO2 OE2 CN2
EC
002aad561
Fig 21. Comparator input and output connections (P89LPC9351/9361)
7.26.1 Internal reference voltage
An internal reference voltage generator may supply a default reference when a single comparator input pin is used. The value of the internal reference voltage, referred to as Vref(bg), is 1.23 V 10 %.
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7.26.2 Comparator interrupt
Each comparator has an interrupt flag contained in its configuration register. This flag is set whenever the comparator output changes state. The flag may be polled by software or may be used to generate an interrupt. The two comparators use one common interrupt vector. If both comparators enable interrupts, after entering the interrupt service routine, the user needs to read the flags to determine which comparator caused the interrupt.
7.26.3 Comparators and power reduction modes
Either or both comparators may remain enabled when Power-down or Idle mode is activated, but both comparators are disabled automatically in Total Power-down mode. If a comparator interrupt is enabled (except in Total Power-down mode), a change of the comparator output state will generate an interrupt and wake-up the processor. If the comparator output to a pin is enabled, the pin should be configured in the push-pull mode in order to obtain fast switching times while in Power-down mode. The reason is that with the oscillator stopped, the temporary strong pull-up that normally occurs during switching on a quasi-bidirectional port pin does not take place. Comparators consume power in Power-down and Idle modes, as well as in the normal operating mode. This fact should be taken into account when system power consumption is an issue. To minimize power consumption, the user can disable the comparators via PCONA.5, or put the device in Total Power-down mode.
7.27 KBI
The Keypad Interrupt function (KBI) is intended primarily to allow a single interrupt to be generated when Port 0 is equal to or not equal to a certain pattern. This function can be used for bus address recognition or keypad recognition. The user can configure the port via SFRs for different tasks. The Keypad Interrupt Mask Register (KBMASK) is used to define which input pins connected to Port 0 can trigger the interrupt. The Keypad Pattern Register (KBPATN) is used to define a pattern that is compared to the value of Port 0. The Keypad Interrupt Flag (KBIF) in the Keypad Interrupt Control Register (KBCON) is set when the condition is matched while the Keypad Interrupt function is active. An interrupt will be generated if enabled. The PATN_SEL bit in the Keypad Interrupt Control Register (KBCON) is used to define equal or not-equal for the comparison. In order to use the Keypad Interrupt as an original KBI function like in P87LPC76x series, the user needs to set KBPATN = 0FFH and PATN_SEL = 1 (not equal), then any key connected to Port 0 which is enabled by the KBMASK register will cause the hardware to set KBIF and generate an interrupt if it has been enabled. The interrupt may be used to wake-up the CPU from Idle or Power-down modes. This feature is particularly useful in handheld, battery-powered systems that need to carefully manage power consumption yet also need to be convenient to use. In order to set the flag and cause an interrupt, the pattern on Port 0 must be held longer than six CCLKs.
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7.28 Watchdog timer
The watchdog timer causes a system reset when it underflows as a result of a failure to feed the timer prior to the timer reaching its terminal count. It consists of a programmable 12-bit prescaler, and an 8-bit down counter. The down counter is decremented by a tap taken from the prescaler. The clock source for the prescaler can be the PCLK, the nominal 400 kHz watchdog oscillator or low speed crystal oscillator. The watchdog timer can only be reset by a power-on reset. When the watchdog feature is disabled, it can be used as an interval timer and may generate an interrupt. Figure 22 shows the watchdog timer in Watchdog mode. Feeding the watchdog requires a two-byte sequence. If PCLK is selected as the watchdog clock and the CPU is powered down, the watchdog is disabled. The watchdog timer has a time-out period that ranges from a few s to a few seconds. Please refer to the P89LPC9331/9341/9351/9361 User manual for more details.
WDL (C1H)
MOV WFEED1, #0A5H MOV WFEED2, #05AH PCLK watchdog oscillator
0 0 1 crystal oscillator 1 XTALWD SHADOW REGISTER /32 PRESCALER 8-BIT DOWN COUNTER reset(1)
WDCON (A7H)
PRE2
PRE1
PRE0
-
-
WDRUN
WDTOF
WDCLK
002aae015
(1) Watchdog reset can also be caused by an invalid feed sequence, or by writing to WDCON not immediately followed by a feed sequence.
Fig 22. Watchdog timer in Watchdog mode (WDTE = 1)
7.29 Additional features
7.29.1 Software reset
The SRST bit in AUXR1 gives software the opportunity to reset the processor completely, as if an external reset or watchdog reset had occurred. Care should be taken when writing to AUXR1 to avoid accidental software resets.
7.29.2 Dual data pointers
The dual Data Pointers (DPTR) provides two different Data Pointers to specify the address used with certain instructions. The DPS bit in the AUXR1 register selects one of the two Data Pointers. Bit 2 of AUXR1 is permanently wired as a logic 0 so that the DPS bit may be toggled (thereby switching Data Pointers) simply by incrementing the AUXR1 register, without the possibility of inadvertently altering other bits in the register.
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7.29.3 Data EEPROM (P89LPC9351/9361)
The P89LPC9351/9361 has 512 bytes of on-chip Data EEPROM. The Data EEPROM is SFR based, byte readable, byte writable, and erasable (via row fill and sector fill). The user can read, write and fill the memory via SFRs and one interrupt. This Data EEPROM provides 100,000 minimum erase/program cycles for each byte.
* Byte mode: In this mode, data can be read and written one byte at a time. * Row fill: In this mode, the addressed row (64 bytes) is filled with a single value. The
entire row can be erased by writing 00H.
* Sector fill: In this mode, all 512 bytes are filled with a single value. The entire sector
can be erased by writing 00H. After the operation finishes, the hardware will set the EEIF bit, which if enabled will generate an interrupt. The flag is cleared by software. Remark: When voltage supply is lower than 2.4 V, the BOD EEPROM is tripped and Data EEPROM program or erase is blocked. EWERR1 and EWERR0 bits are used to indicate the write error for BOD EEPROM. Both can be cleared by power-on reset, watchdog reset or software write.
7.30 Flash program memory
7.30.1 General description
The P89LPC9331/9341/9351/9361 flash memory provides in-circuit electrical erasure and programming. The flash can be erased, read, and written as bytes. The Sector and Page Erase functions can erase any flash sector (1 kB) or page (64 bytes). The Chip Erase operation will erase the entire program memory. ICP using standard commercial programmers is available. In addition, IAP and byte-erase allows code memory to be used for non-volatile data storage. On-chip erase and write timing generation contribute to a user-friendly programming interface. The P89LPC9331/9341/9351/9361 flash reliably stores memory contents even after 100,000 erase and program cycles. The cell is designed to optimize the erase and programming mechanisms. The P89LPC9331/9341/9351/9361 uses VDD as the supply voltage to perform the Program/Erase algorithms. When voltage supply is lower than 2.4 V, the BOD FLASH is tripped and flash erase/program is blocked.
7.30.2 Features
* * * * *
Programming and erase over the full operating voltage range. Byte erase allows code memory to be used for data storage. Read/Programming/Erase using ISP/IAP/ICP. Internal fixed boot ROM, containing low-level IAP routines available to user code. Default loader providing ISP via the serial port, located in upper end of user program memory. memory space, providing flexibility to the user.
* Boot vector allows user-provided flash loader code to reside anywhere in the flash * Any flash program/erase operation in 2 ms. * Programming with industry-standard commercial programmers.
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* Programmable security for the code in the flash for each sector. * 100,000 typical erase/program cycles for each byte. * 10 year minimum data retention.
7.30.3 Flash organization
The program memory consists of sixteen 1 kB sectors on the P89LPC9361 devices and eight 1 kB sectors on the P89LPC9341/9351 devices and four 1 kB sectors on the P89LPC9331 device. Each sector can be further divided into 64-byte pages. In addition to sector erase, page erase, and byte erase, a 64-byte page register is included which allows from 1 byte to 64 bytes of a given page to be programmed at the same time, substantially reducing overall programming time.
7.30.4 Using flash as data storage
The flash code memory array of this device supports individual byte erasing and programming. Any byte in the code memory array may be read using the MOVC instruction, provided that the sector containing the byte has not been secured (a MOVC instruction is not allowed to read code memory contents of a secured sector). Thus any byte in a non-secured sector may be used for non-volatile data storage.
7.30.5 Flash programming and erasing
Four different methods of erasing or programming of the flash are available. The flash may be programmed or erased in the end-user application (IAP) under control of the application's firmware. Another option is to use the ICP mechanism. This ICP system provides for programming through a serial clock/serial data interface. As shipped from the factory, the upper 512 bytes of user code space contains a serial ISP routine allowing for the device to be programmed in circuit through the serial port. The flash may also be programmed or erased using a commercially available EPROM programmer which supports this device. This device does not provide for direct verification of code memory contents. Instead, this device provides a 32-bit CRC result on either a sector or the entire user code space. Remark: When voltage supply is lower than 2.4 V, the BOD FLASH is tripped and flash erase/program is blocked.
7.30.6 ICP
ICP is performed without removing the microcontroller from the system. The ICP facility consists of internal hardware resources to facilitate remote programming of the P89LPC9331/9341/9351/9361 through a two-wire serial interface. The NXP ICP facility has made in-circuit programming in an embedded application - using commercially available programmers - possible with a minimum of additional expense in components and circuit board area. The ICP function uses five pins. Only a small connector needs to be available to interface your application to a commercial programmer in order to use this feature. Additional details may be found in the P89LPC9331/9341/9351/9361 User manual.
7.30.7 IAP
IAP is performed in the application under the control of the microcontroller's firmware. The IAP facility consists of internal hardware resources to facilitate programming and erasing. The NXP IAP has made in-application programming in an embedded application possible
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without additional components. Two methods are available to accomplish IAP. A set of predefined IAP functions are provided in a Boot ROM and can be called through a common interface, PGM_MTP. Several IAP calls are available for use by an application program to permit selective erasing and programming of flash sectors, pages, security bits, configuration bytes, and device ID. These functions are selected by setting up the microcontroller's registers before making a call to PGM_MTP at FF03H. The Boot ROM occupies the program memory space at the top of the address space from FF00H to FEFFH, thereby not conflicting with the user program memory space. In addition, IAP operations can be accomplished through the use of four SFRs consisting of a control/status register, a data register, and two address registers. Additional details may be found in the P89LPC9331/9341/9351/9361 User manual.
7.30.8 ISP
ISP is performed without removing the microcontroller from the system. The ISP facility consists of a series of internal hardware resources coupled with internal firmware to facilitate remote programming of the P89LPC9331/9341/9351/9361 through the serial port. This firmware is provided by NXP and embedded within each P89LPC9331/9341/9351/9361 device. The NXP ISP facility has made in-system programming in an embedded application possible with a minimum of additional expense in components and circuit board area. The ISP function uses five pins (VDD, VSS, TXD, RXD, and RST). Only a small connector needs to be available to interface your application to an external circuit in order to use this feature.
7.30.9 Power-on reset code execution
The P89LPC9331/9341/9351/9361 contains two special flash elements: the Boot Vector and the Boot Status bit. Following reset, the P89LPC9331/9341/9351/9361 examines the contents of the Boot Status bit. If the Boot Status bit is set to zero, power-up execution starts at location 0000H, which is the normal start address of the user's application code. When the Boot Status bit is set to a value other than zero, the contents of the Boot Vector are used as the high byte of the execution address and the low byte is set to 00H. Table 10 shows the factory default Boot Vector setting for these devices. A factory-provided bootloader is pre-programmed into the address space indicated and uses the indicated bootloader entry point to perform ISP functions. This code can be erased by the user. Remark: Users who wish to use this loader should take precautions to avoid erasing the 1 kB sector that contains this bootloader. Instead, the page erase function can be used to erase the first eight 64-byte pages located in this sector. A custom bootloader can be written with the Boot Vector set to the custom bootloader, if desired.
Table 10. Device Default boot vector values and ISP entry points Default boot vector 0FH Default bootloader entry point 0F00H Default bootloader code range 0E00H to 0FFFH 1 kB sector range 0C00H to 0FFFH
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Default boot vector values and ISP entry points ...continued Default boot vector 1FH 1FH 3FH Default bootloader entry point 1F00H 1F00H 3F00H Default bootloader code range 1E00H to 1FFFH 1E00H to 1FFFH 3E00H to 3FFFH 1 kB sector range 1C00H to 1FFFH 1C00H to 1FFFH 3C00H to 3FFFH
Table 10. Device
P89LPC9341 P89LPC9351 P89LPC9361
7.30.10 Hardware activation of the bootloader
The bootloader can also be executed by forcing the device into ISP mode during a power-on sequence (see the P89LPC9331/9341/9351/9361 User manual for specific information). This has the same effect as having a non-zero status byte. This allows an application to be built that will normally execute user code but can be manually forced into ISP operation. If the factory default setting for the boot is changed, it will no longer point to the factory pre-programmed ISP bootloader code. After programming the flash, the status byte should be programmed to zero in order to allow execution of the user's application code beginning at address 0000H.
7.31 User configuration bytes
Some user-configurable features of the P89LPC9331/9341/9351/9361 must be defined at power-up and therefore cannot be set by the program after start of execution. These features are configured through the use of the flash byte UCFG1 and UCFG2. Please see the P89LPC9331/9341/9351/9361 User manual for additional details.
7.32 User sector security bytes
There are 4/8/6 User Sector Security Bytes on the P89LPC9331/9341/9351/9361. Each byte corresponds to one sector. Please see the P89LPC9331/9341/9351/9361 User manual for additional details.
8. ADC
8.1 General description
The P89LPC9331/9341/9351/9361 has two 8-bit, 4-channel multiplexed successive approximation analog-to-digital converter modules. An on-chip temperature sensor is integrated within ADC0 and operates over wide temperature. In P89LPC9351/9361, two high-speed programmable gain amplifiers (PGA) are integrated. The PGAs provide selectable gains of 2x, 4x, 8x, or 16x. A block diagram of the ADC is shown in Figure 23 and Figure 24. Each ADC consists of a 4-input multiplexer which feeds a sample-and-hold circuit providing an input signal to comparator inputs. The control logic in combination with the SAR drives a digital-to-analog converter which provides the other input to the comparator. The output of the comparator is fed to the SAR.
8.2 Features and benefits
Two 8-bit, 4-channel multiplexed input, successive approximation ADCs.
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Programmable Gain Amplifier (PGA) with selectable gains of 2x, 4x, 8x, or 16x. (P89LPC9351/9361) On-chip wide range temperature sensor. Four result registers for each A/D. Six operating modes: Fixed channel, single conversion mode. Fixed channel, continuous conversion mode. Auto scan, single conversion mode. Auto scan, continuous conversion mode. Dual channel, continuous conversion mode. Single step mode. Four conversion start modes: Timer triggered start. Start immediately. Edge triggered. Dual start immediately. 8-bit conversion time of 1.61 s at an A/D clock of 8.0 MHz. Interrupt or polled operation. Boundary limits interrupt. DAC output to a port pin with high output impedance. Clock divider. Power-down mode.
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8.3 Block diagram
AD00 AD01 AD02 AD03 Vref(bg) Vsen input MUX
Anin00 Anin01 Anin02 Anin03
input MUX comp SAR
DAC0
8
AD10 AD11 AD12 AD13
Anin10 Anin11 Anin12 Anin13
input MUX comp SAR
CONTROL LOGIC
DAC1
8
CCLK 4 to comparators
002aae463
Fig 23. P89LPC9331/9341 ADC block diagram
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AD00 AD01 AD02 AD03 Vref(bg) Vsen
input MUX PGA0 Anin00 Anin01 Anin02 Anin03 comp + SAR -
DAC0
8
AD10 AD11 AD12 AD13
PGA1
Anin10 Anin11 Anin12 Anin13
input MUX comp + SAR -
CONTROL LOGIC
DAC1
8
CCLK 4 to comparators
002aad576
Fig 24. P89LPC9351/9361 ADC block diagram
8.4 PGA (P89LPC9351/9361)
Additional PGA module is integrated in each ADC module to improve the effective resolution of the ADC. A single channel can be selected for amplification. The gain of PGA can be programmable to 2, 4, 8 and 16. Please refer to Table 12 "Static characteristics" for detailed specifications. Register PGACONx and PGACONxB are used to for PGA configuration. Register PGAxTRIM2X4X and PGAxTRIM8X16X provide trim value of PGA gain level. As power-on, default trim value for each gain setting is loaded into the PGA trim registers. For accurate measurements, offset calibration is required. Please see the P89LPC9331/9341/9351/9361 User manual for detail configuration, calibration, and usage information.
8.5 Temperature sensor
An on-chip wide-temperature range temperature sensor is integrated with ADC0 module. It provides temperature sensing capability of -40 C ~ 85 C. It is necessary to measure the 1.2 V reference voltage via the ADC before measuring temperature. In P89LPC9351/9361, the reference voltage, temperature sensor and AD03 input pin multiplex one input to PGA0. Please see the P89LPC9331/9341/9351/9361 User manual for detail usage of temperature sensor.
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8.6 ADC operating modes
8.6.1 Fixed channel, single conversion mode
A single input channel can be selected for conversion. A single conversion will be performed and the result placed in the result register pair which corresponds to the selected input channel. An interrupt, if enabled, will be generated after the conversion completes. In P89LPC9351/9361, in fixed channel mode, the PGA channel selection is dependent on the ADC channel selection. If PGA is enabled, all the selected channels for A/D conversion will be amplified and the gain amplify level is the same.
8.6.2 Fixed channel, continuous conversion mode
A single input channel can be selected for continuous conversion. The results of the conversions will be sequentially placed in the four result register. The user may select whether an interrupt can be generated after every four conversions. Additional conversion results will again cycle through the four result register, overwriting the previous results. Continuous conversions continue until terminated by the user. In P89LPC9351/9361, in fixed channel mode, the PGA channel selection is independent and can be different to A/D conversion channel selection. If different, the gain of the selected ADC channel is 1.
8.6.3 Auto scan, single conversion mode
Any combination of the four input channels can be selected for conversion. A single conversion of each selected input will be performed and the result placed in the result register which corresponds to the selected input channel. An interrupt, if enabled, will be generated after all selected channels have been converted. If only a single channel is selected this is equivalent to single channel, single conversion mode. In P89LPC9351/9361, in auto scan mode, the PGA channel selection is dependent on the ADC channel selection. If PGA is enabled, all the selected channel for A/D conversion will be amplified and the gain amplify level is the same.
8.6.4 Auto scan, continuous conversion mode
Any combination of the four input channels can be selected for conversion. A conversion of each selected input will be performed and the result placed in the result register which corresponds to the selected input channel. An interrupt, if enabled, will be generated after all selected channels have been converted. The process will repeat starting with the first selected channel. Additional conversion results will again cycle through the eight result register pairs, overwriting the previous results. Continuous conversions continue until terminated by the user. In P89LPC9351/9361, in auto scan mode, the PGA channel selection is dependent on the ADC channel selection. If PGA is enabled, all the selected channel for A/D conversion will be amplified and the gain amplify level is the same.
8.6.5 Dual channel, continuous conversion mode
This is a variation of the auto scan continuous conversion mode where conversion occurs on two user-selectable inputs. The result of the conversion of the first channel is placed in the result register, ADxDAT0. The result of the conversion of the second channel is placed
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in result register, ADxDAT1. The first channel is again converted and its result stored in ADxDAT2. The second channel is again converted and its result placed in ADxDAT3. An interrupt is generated, if enabled, after every set of four conversions (two conversions per channel). In P89LPC9351/9361, in dual channel mode, the PGA channel selection is independent and can be different to A/D conversion channel selection. If different, the gain of the selected ADC channel is 1.
8.6.6 Single step mode
This special mode allows `single-stepping' in an auto scan conversion mode. Any combination of the four input channels can be selected for conversion. After each channel is converted, an interrupt is generated, if enabled, and the A/D waits for the next start condition. May be used with any of the start modes. In P89LPC9351/9361, in single step mode, the PGA channel selection is independent and can be different to A/D conversion channel selection. If different, the gain of the selected ADC channel is 1.
8.7 Conversion start modes
8.7.1 Timer triggered start
An A/D conversion is started by the overflow of Timer 0. Once a conversion has started, additional Timer 0 triggers are ignored until the conversion has completed. The Timer triggered start mode is available in all ADC operating modes.
8.7.2 Start immediately
Programming this mode immediately starts a conversion. This start mode is available in all ADC operating modes.
8.7.3 Edge triggered
An A/D conversion is started by rising or falling edge of P1.4. Once a conversion has started, additional edge triggers are ignored until the conversion has completed. The edge triggered start mode is available in all ADC operating modes.
8.7.4 Dual start immediately
Programming this mode starts a synchronized conversion of both A/D converters. This start mode is available in all A/D operating modes. Both A/D converters must be in the same operating mode. In the continuous conversion modes, both A/D converters must select an identical number of channels. Any trigger of either A/D will start a simultaneous conversion of both A/Ds.
8.8 Boundary limits interrupt
Each of the A/D converters has both a high and low boundary limit register. The user may select whether an interrupt is generated when the conversion result is within (or equal to) the high and low boundary limits or when the conversion result is outside the boundary limits. An interrupt will be generated, if enabled, if the result meets the selected interrupt criteria. The boundary limit may be disabled by clearing the boundary limit interrupt enable.
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An early detection mechanism exists when the interrupt criteria has been selected to be outside the boundary limits. In this case, after the four MSBs have been converted, these four bits are compared with the four MSBs of the boundary high and low registers. If the four MSBs of the conversion meet the interrupt criteria (i.e., outside the boundary limits) an interrupt will be generated, if enabled. If the four MSBs do not meet the interrupt criteria, the boundary limits will again be compared after all 8 bits have been converted. The boundary status register (BNDSTA0) flags the channels which caused a boundary interrupt.
8.9 DAC output to a port pin with high output impedance
Each ADC's DAC block can be output to a port pin. In this mode, the ADxDAT3 register is used to hold the value fed to the DAC. After a value has been written to the DAC (written to ADxDAT3), the DAC output will appear on the channel 3 pin.
8.10 Clock divider
The ADC requires that its internal clock source be in the range of 320 kHz to 8 MHz to maintain accuracy. A programmable clock divider that divides the clock from 1 to 8 is provided for this purpose.
8.11 Power-down and Idle mode
In Idle mode the ADC, if enabled, will continue to function and can cause the device to exit Idle mode when the conversion is completed if the A/D interrupt is enabled. In Power-down mode or Total Power-down mode, the A/D, PGA and temperature sensor do not function. If the PGAs, temperature sensor or the A/D are enabled, they will consume power. Power can be reduced by disabling the PGA, temperature sensor and A/D.
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9. Limiting values
Table 11. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Tamb(bias) Tstg IOH(I/O) IOL(I/O) II/Otot(max) Vxtal Vn Ptot(pack) Parameter bias ambient temperature storage temperature HIGH-level output current per input/output pin LOW-level output current per input/output pin maximum total input/output current crystal voltage voltage on any other pin total power dissipation (per package) on XTAL1, XTAL2 pin to VSS except XTAL1, XTAL2 to VSS based on package heat transfer, not device power consumption human body model; all pins charged device model; all pins
[1] The following applies to Table 11: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) Parameters are valid over ambient temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. [2] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.
[2]
Conditions
Min -55 -65 -0.5 -
Max +125 +150 20 20 100 VDD + 0.5 +5.5 1.5
Unit C C mA mA mA V V W
VESD
electrostatic discharge voltage
-3000 -700
+3000 +700
V V
system frequency (MHz) 18
12
2.4
2.7
3.0 VDD (V)
3.3
3.6
002aae351
Fig 25. Frequency vs. supply voltage
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10. Static characteristics
Table 12. Static characteristics VDD = 2.4 V to 3.6 V unless otherwise specified. Tamb = -40 C to +85 C for industrial applications, -40 C to +125 C extended, unless otherwise specified. Symbol IDD(oper) IDD(idle) IDD(pd) IDD(tpd) Parameter operating supply current Idle mode supply current Power-down mode supply current total Power-down mode supply current Conditions VDD = 3.6 V; fosc = 12 MHz VDD = 3.6 V; fosc = 18 MHz VDD = 3.6 V; fosc = 12 MHz VDD = 3.6 V; fosc = 18 MHz VDD = 3.6 V; voltage comparators powered down all devices except P89LPC9331HDH; VDD = 3.6 V P89LPC9331HDH only; VDD = 3.6 V (dV/dt)r VPOR VDDR Vth(HL) VIL Vth(LH) VIH Vhys VOL rise rate power-on reset voltage data retention supply voltage HIGH-LOW threshold voltage LOW-level input voltage LOW-HIGH threshold voltage HIGH-level input voltage hysteresis voltage LOW-level output voltage except SCL, SDA SCL, SDA only except SCL, SDA SCL, SDA only port 1 IOL = 20 mA; VDD = 2.4 V to 3.6 V all ports, all modes except high-Z IOL = 3.2 mA; VDD = 2.4 V to 3.6 V all ports, all modes except high-Z VOH HIGH-level output voltage IOH = -20 A; VDD = 2.4 V to 3.6 V; all ports, quasi-bidirectional mode IOH = -3.2 mA; VDD = 2.4 V to 3.6 V; all ports, push-pull mode IOH = -10 mA; VDD = 2.4 V to 3.6 V; all ports, push-pull mode Vxtal Vn Ciss crystal voltage voltage on any other pin input capacitance
Rev. 5 -- 10 January 2011
[6] [2] [2] [3] [3] [4]
Min -
Typ[1] 10 14 2 3 20 0.5
Max 15 23 3.5 5 40 5
Unit mA mA mA mA A A
[5]
[5]
5 1.5 0.22VDD -0.5 0.7VDD -
0.4VDD 0.6VDD 0.2VDD 0.6
25 5000 0.5 0.3VDD 0.7VDD 5.5 1.0
A V/S V V V V V V V V
of VDD; to ensure power-on reset signal
[6]
-
0.2
0.3
V
VDD - 0.3
VDD - 0.2
-
V
VDD - 0.7
VDD - 0.4
-
V
-
3.2
-
V
on XTAL1, XTAL2 pins; with respect to VSS except XTAL1, XTAL2, VDD; with respect to VSS
[7]
-0.5 -0.5 -
-
+4.0 +5.5 15
V V pF
66 of 94
[8]
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P89LPC9331/9341/9351/9361
8-bit microcontroller with accelerated two-clock 80C51 core
Table 12. Static characteristics ...continued VDD = 2.4 V to 3.6 V unless otherwise specified. Tamb = -40 C to +85 C for industrial applications, -40 C to +125 C extended, unless otherwise specified. Symbol IIL ILI ITHL Parameter LOW-level input current input leakage current HIGH-LOW transition current Conditions VI = 0.4 V VI = VIL, VIH, or Vth(HL) all ports; VI = 1.5 V at VDD = 3.6 V pin RST
[9] [10] [11]
Min -30 10 1.19 -
Typ[1] 1.23 10
Max -80 1 -450 30 1.27 20
Unit A A A k V ppm/ C
RRST_N(int) internal pull-up resistance on pin RST Vref(bg) TCbg band gap reference voltage band gap temperature coefficient
[1] [2] [3] [4] [5] [6] [7]
Typical ratings are not guaranteed. The values listed are at room temperature, 3 V. The IDD(oper) specification is measured using an external clock with code while(1) {} executed from on-chip flash. The IDD(idle) specification is measured using an external clock with no active peripherals, with the following functions disabled: real-time clock and watchdog timer. The IDD(pd) specification is measured using internal RC oscillator with the following functions disabled: comparators, real-time clock, and watchdog timer. The IDD(tpd) specification is measured using an external clock with the following functions disabled: comparators, real-time clock, brownout detect, and watchdog timer. See Section 9 "Limiting values" for steady state (non-transient) limits on IOL or IOH. If IOL/IOH exceeds the test condition, VOL/VOH may exceed the related specification. This specification can be applied to pins which have A/D input or analog comparator input functions when the pin is not being used for those analog functions. When the pin is being used as an analog input pin, the maximum voltage on the pin must be limited to 4.0 V with respect to VSS. Pin capacitance is characterized but not tested. Measured with port in quasi-bidirectional mode.
[8] [9]
[10] Measured with port in high-impedance mode. [11] Port pins source a transition current when used in quasi-bidirectional mode and externally driven from logic 1 to logic 0. This current is highest when VI is approximately 2 V.
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10.1 Current characteristics
Note: The graphs provided are a statistical summary based on a limited number of samples and only for information purposes. The performance characteristics listed are not tested or guaranteed.
16 IDD (mA) 12
002aae363
18 MHz
12 MHz 8 8 MHz 6 MHz 4 4 MHz 2 MHz 1 MHz 32 kHz 3.6 VDD (V)
0 2.4
2.8
3.2
Test conditions: normal mode, code while(1) {} executed from on-chip flash; using an external clock.
Fig 26. IDD(oper) vs. frequency at +25 C
16 IDD (mA) 12
002aae364
18 MHz
12 MHz 8 8 MHz 6 MHz 4 4 MHz 2 MHz 1 MHz 32 kHz 3.6 VDD (V)
0 2.4
2.8
3.2
Test conditions: normal mode, code while(1) {} executed from on-chip flash; using an external clock.
Fig 27. IDD(oper) vs. frequency at -40 C
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16 IDD (mA) 12
002aae365
18 MHz
12 MHz 8 8 MHz 6 MHz 4 4 MHz 2 MHz 1 MHz 32 kHz 3.6 VDD (V)
0 2.4
2.8
3.2
Test conditions: normal mode, code while(1) {} executed from on-chip flash; using an external clock.
Fig 28. IDD(oper) vs. frequency at +85 C
5.0 IDD (mA) 4.0
002aae366
18 MHz
12 MHz 3.0 8 MHz 2.0 6 MHz 4 MHz 1.0 2 MHz 1 MHz 32 kHz 2.8 3.2 VDD (V) 3.6
0.0 2.4
Test conditions: idle mode entered executing code from on-chip flash; using an external clock with no active peripherals, with the following functions disabled: real-time clock and watchdog timer.
Fig 29. IDD(idle) vs. frequency at +25 C
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5.0 IDD (mA) 4.0
002aae367
18 MHz
12 MHz 3.0 8 MHz 2.0 6 MHz 4 MHz 1.0 2 MHz 1 MHz 32 kHz 2.8 3.2 VDD (V) 3.6
0.0 2.4
Test conditions: idle mode entered executing code from on-chip flash; using an external clock with no active peripherals, with the following functions disabled: real-time clock and watchdog timer.
Fig 30. IDD(idle) vs. frequency at -40 C
5.0 IDD (mA) 4.0
002aae368
18 MHz
12 MHz 3.0 8 MHz 2.0 6 MHz 4 MHz 1.0 2 MHz 1 MHz 32 kHz 2.8 3.2 VDD (V) 3.6
0.0 2.4
Test conditions: idle mode entered executing code from on-chip flash; using an external clock with no active peripherals, with the following functions disabled: real-time clock and watchdog timer.
Fig 31. IDD(idle) vs. frequency at +85 C
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20.0 IDD (A) 18.0
002aae369
(1)
16.0
(2)
14.0
(3)
12.0
10.0 2.4
2.8
3.2 VDD (V)
3.6
Test conditions: power-down mode, using internal RC oscillator with the following functions disabled: comparators, real-time clock, and watchdog timer. (1) +85 C (2) +25 C (3) -40 C
Fig 32. IDD(pd) vs. VDD
1.2 IDD (A) 0.8
002aae370 (1)
0.4
(2)
(3)
0.0 2.4
2.8
3.2 VDD (V)
3.6
Test conditions: Total power-down mode, using internal RC oscillator with the following functions disabled: comparators, brownout detect, real-time clock, and watchdog timer. (1) +85 C (2) -40 C (3) +25 C
Fig 33. IDD(tpd) vs. VDD
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10.2 Internal RC/watchdog oscillator characteristics
Note: The graphs provided are a statistical summary based on a limited number of samples and only for information purposes. The performance characteristics listed are not tested or guaranteed.
0.2 frequency deviation (%) 0.1
002aae344
0
-0.1
-0.2 2.4
2.8
3.2 VDD (V)
3.6
Central frequency of internal RC oscillator = 7.3728 MHz
Fig 34. Average internal RC oscillator frequency vs. VDD at +25 C
0.2 frequency deviation (%) 0.1
002aae346
0
-0.1
-0.2 2.4
2.8
3.2 VDD (V)
3.6
Note: Central frequency of internal RC oscillator = 7.3728 MHz
Fig 35. Average internal RC oscillator frequency vs. VDD at -40 C
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8-bit microcontroller with accelerated two-clock 80C51 core
0.2 frequency deviation (%) 0
002aae347
-0.2
-0.4
-0.6 2.4
2.8
3.2 VDD (V)
3.6
Central frequency of internal RC oscillator = 7.3728 MHz
Fig 36. Average internal RC oscillator frequency vs. VDD at +85 C
2.5 frequency deviation (%) 1.5
002aae348
0.5
-0.5
-1.5 2.4
2.8
3.2 VDD (V)
3.6
Central frequency of watchdog oscillator = 400 KHz
Fig 37. Average watchdog oscillator frequency vs. VDD at +25 C
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0.5 frequency deviation (%) -0.5
002aae349
-1.5
-2.5
-3.5 2.4
2.8
3.2 VDD (V)
3.6
Central frequency of watchdog oscillator = 400 KHz
Fig 38. Average watchdog oscillator frequency vs. VDD at -40 C
1.5 frequency deviation (%) 0.5
002aae350
-0.5
-1.5
-2.5 2.4
2.8
3.2 VDD (V)
3.6
Central frequency of watchdog oscillator = 400 KHz
Fig 39. Average watchdog oscillator frequency vs. VDD at +85 C
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10.3 BOD characteristics
Table 13. BOD static characteristics VDD = 2.4 V to 3.6 V unless otherwise specified. Tamb = -40 C to +85 C for industrial applications, -40 C to +125 C extended, unless otherwise specified. Symbol Vtrip Parameter trip voltage Conditions falling stage BOICFG1, BOICFG0 = 01 BOICFG1, BOICFG0 = 10 BOICFG1, BOICFG0 = 11 rising stage BOICFG1, BOICFG0 = 01 BOICFG1, BOICFG0 = 10 BOICFG1, BOICFG0 = 11 BOD reset Vtrip trip voltage falling stage BOE1, BOE0 = 01 BOE1, BOE0 = 10 BOE1, BOE0 = 11 rising stage BOE1, BOE0 = 01 BOE1, BOE0 = 10 BOE1, BOE0 = 11 BOD EEPROM/FLASH Vtrip trip voltage falling stage rising stage
[1] Typical ratings are not guaranteed. The values listed are at room temperature, 3 V.
Min
Typ[1]
Max
Unit
BOD interrupt 2.25 2.60 3.10 2.40 2.70 3.10 2.55 2.80 3.40 2.60 2.90 3.40 V V V V V V
2.10 2.35 2.90 2.20 2.45 2.90 2.25 2.35
-
2.30 2.50 3.20 2.40 2.60 3.30 2.60 2.65
V V V V V V V V
VDD Vtrip (BOF/BOIF set by hardware) (BOF/BOIF can be cleared in software)
BOF/BOIF
002aae352
Fig 40. BOD interrupt/reset characteristics
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11. Dynamic characteristics
Table 14. Dynamic characteristics (12 MHz) VDD = 2.4 V to 3.6 V unless otherwise specified. Tamb = -40 C to +85 C for industrial applications, -40 C to +125 C extended, unless otherwise specified.[1][2] Symbol fosc(RC) Parameter internal RC oscillator frequency Conditions nominal f = 7.3728 MHz trimmed to 1 % at Tamb = 25 C; clock doubler option = OFF (default) nominal f = 14.7456 MHz; clock doubler option = ON, VDD = 2.7 V to 3.6 V fosc(WD) fosc Tcy(clk) fCLKLP Glitch filter tgr tsa glitch rejection time signal acceptance time P1.5/RST pin any pin except P1.5/RST P1.5/RST pin any pin except P1.5/RST External clock tCHCX tCLCX tCLCH tCHCL TXLXL tQVXH tXHQX tXHDX tXHDV clock HIGH time clock LOW time clock rise time clock fall time serial port clock cycle time output data set-up to clock rising edge time output data hold after clock rising edge time input data hold after clock rising edge time input data valid to clock rising edge time SPI operating frequency slave master 0 CCLK CCLK 6 4
Variable clock Min 7.189 Max 7.557
fosc = 12 MHz Min 7.189 Max
Unit
7.557 MHz
14.378
15.114
14.378 15.114 MHz
internal watchdog oscillator frequency oscillator frequency clock cycle time low-power select clock frequency
Tamb = 25 C
380 0
420 12 8
380 -
420 -
kHz MHz ns MHz
see Figure 41
83 0
125 50 33 33 16Tcy(clk) 13Tcy(clk) 150
50 15 Tcy(clk) - tCLCX Tcy(clk) - tCHCX 8 8 Tcy(clk) + 20 0 -
125 50 33 33 1333 1083 150
50 15 8 8 103 0 -
ns ns ns ns ns ns ns ns ns ns ns ns ns
see Figure 41 see Figure 41 see Figure 41 see Figure 41 see Figure 42 see Figure 42 see Figure 42 see Figure 42 see Figure 42
Shift register (UART mode 0)
SPI interface fSPI 0 2.0 3.0 MHz MHz
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Table 14. Dynamic characteristics (12 MHz) ...continued VDD = 2.4 V to 3.6 V unless otherwise specified. Tamb = -40 C to +85 C for industrial applications, -40 C to +125 C extended, unless otherwise specified.[1][2] Symbol TSPICYC Parameter SPI cycle time slave master tSPILEAD tSPILAG tSPICLKH SPI enable lead time slave SPI enable lag time slave SPICLK HIGH time master slave tSPICLKL SPICLK LOW time master slave tSPIDSU tSPIDH tSPIA tSPIDIS tSPIDV SPI data set-up time master or slave SPI data hold time master or slave SPI access time slave SPI disable time slave SPI enable to output data valid time slave master tSPIOH tSPIR SPI output data hold time SPI rise time SPI outputs (SPICLK, MOSI, MISO) SPI inputs (SPICLK, MOSI, MISO, SS) tSPIF SPI fall time SPI outputs (SPICLK, MOSI, MISO) SPI inputs (SPICLK, MOSI, MISO, SS)
[1] [2]
Conditions see Figure 43, 44, 45, 46
6 4
Variable clock Min Max 120 240
fosc = 12 MHz Min 500 333 250 250 165 250 165 250 100 100 0 Max 120 240
Unit
CCLK CCLK
ns ns ns ns ns ns ns ns ns ns ns ns
see Figure 45, 46 250 see Figure 45, 46 250 see Figure 43, 44, 45, 46
2 3 CCLK CCLK
see Figure 43, 44, 45, 46
2 3 CCLK CCLK
see Figure 43, 44, 45, 46 100 see Figure 43, 44, 45, 46 100 see Figure 45, 46 0 see Figure 45, 46 0 see Figure 43, 44, 45, 46 see Figure 43, 44, 45, 46 see Figure 43, 44, 45, 46 see Figure 43, 44, 45, 46 100 2000 100 2000 ns ns 100 2000 100 2000 ns ns 0 240 167 0 240 167 ns ns ns
Parameters are valid over operating temperature range unless otherwise specified. Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz.
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Table 15. Dynamic characteristics (18 MHz) VDD = 3.0 V to 3.6 V unless otherwise specified. Tamb = -40 C to +85 C for industrial applications, -40 C to +125 C extended, unless otherwise specified.[1][2] Symbol Parameter fosc(RC) internal RC oscillator frequency Conditions nominal f = 7.3728 MHz trimmed to 1 % at Tamb = 25 C; clock doubler option = OFF (default) nominal f = 14.7456 MHz; clock doubler option = ON fosc(WD) fosc Tcy(clk) fCLKLP internal watchdog oscillator frequency oscillator frequency clock cycle time low-power select clock frequency glitch rejection time signal acceptance time P1.5/RST pin any pin except P1.5/RST tsa P1.5/RST pin any pin except P1.5/RST External clock tCHCX tCLCX tCLCH tCHCL TXLXL tQVXH tXHQX tXHDX tXHDV clock HIGH time clock LOW time clock rise time clock fall time serial port clock cycle time output data set-up to clock rising edge time output data hold after clock rising edge time input data hold after clock rising edge time input data valid to clock rising edge time SPI operating frequency slave master TSPICYC SPI cycle time slave master see Figure 43, 44, 45, 46
6 4 CCLK CCLK
Variable clock Min 7.189 Max 7.557
fosc = 18 MHz Min 7.189 Max
Unit
7.557 MHz
14.378 380 0
15.114 420 18 8
14.378 15.114 MHz 380 420 kHz MHz ns MHz
Tamb = 25 C
see Figure 41
55 0
Glitch filter tgr 125 50 22 22 16Tcy(clk) 13Tcy(clk) 150 50 15 Tcy(clk) - tCLCX Tcy(clk) - tCHCX 5 5 Tcy(clk) + 20 0 125 50 22 22 888 722 150 50 15 5 5 75 0 ns ns ns ns ns ns ns ns ns ns ns ns ns
see Figure 41 see Figure 41 see Figure 41 see Figure 41 see Figure 42 see Figure 42 see Figure 42 see Figure 42 see Figure 42
Shift register (UART mode 0)
SPI interface fSPI 0 CCLK CCLK
6 4
0 333 222
3.0 4.5 -
MHz MHz ns ns
-
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Table 15. Dynamic characteristics (18 MHz) ...continued VDD = 3.0 V to 3.6 V unless otherwise specified. Tamb = -40 C to +85 C for industrial applications, -40 C to +125 C extended, unless otherwise specified.[1][2] Symbol Parameter tSPILEAD tSPILAG tSPICLKH SPI enable lead time slave SPI enable lag time slave SPICLK HIGH time slave master tSPICLKL SPICLK LOW time slave master tSPIDSU tSPIDH tSPIA tSPIDIS tSPIDV SPI data set-up time master or slave SPI data hold time master or slave SPI access time slave SPI disable time slave SPI enable to output data valid time slave master tSPIOH tSPIR SPI output data hold time SPI rise time SPI outputs (SPICLK, MOSI, MISO) SPI inputs (SPICLK, MOSI, MISO, SS) tSPIF SPI fall time SPI outputs (SPICLK, MOSI, MISO) SPI inputs (SPICLK, MOSI, MISO, SS)
[1] [2]
Conditions see Figure 45, 46
Variable clock Min 250 Max 80 160
fosc = 18 MHz Min 250 250 167 111 167 111 100 100 0 Max 80 160
Unit
ns ns ns ns ns ns ns ns ns ns
see Figure 45, 46 250 see Figure 43, 44, 45, 46
3 2 CCLK CCLK
see Figure 43, 44, 45, 46
3 2 CCLK CCLK
see Figure 43, 44, 45, 46 100 see Figure 43, 44, 45, 46 100 see Figure 45, 46 0 see Figure 45, 46 0 see Figure 43, 44, 45, 46 see Figure 43, 44, 45, 46 see Figure 43, 44, 45, 46 see Figure 43, 44, 45, 46 100 2000 100 2000 ns ns 100 2000 100 2000 ns ns 0 160 111 0 160 111 ns ns ns
Parameters are valid over operating temperature range unless otherwise specified. Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz.
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11.1 Waveforms
tCHCL
tCLCX Tcy(clk)
tCHCX tCLCH
002aaa907
Fig 41. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV)
TXLXL clock tQVXH output data 0 write to SBUF input data clear RI set RI
002aaa906
tXHQX 1 tXHDX 2 3 4 5 6 7
tXHDV
valid valid valid valid valid valid valid
set TI
valid
Fig 42. Shift register mode timing
SS TSPICYC tSPIF tSPICLKH SPICLK (CPOL = 0) (output) tSPIF tSPICLKL tSPIR tSPICLKH SPICLK (CPOL = 1) (output) tSPIDSU MISO (input) tSPIDH LSB/MSB in tSPIOH tSPIDV tSPIR master MSB/LSB out master LSB/MSB out
002aaa908
tSPICLKL
tSPIR
MSB/LSB in tSPIDV
MOSI (output)
tSPIF
Fig 43. SPI master timing (CPHA = 0)
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SS TSPICYC tSPIF tSPICLKL tSPIR tSPICLKH
SPICLK (CPOL = 0) (output) tSPIF SPICLK (CPOL = 1) (output) tSPICLKH tSPICLKL tSPIR
tSPIDSU MISO (input)
tSPIDH LSB/MSB in tSPIOH tSPIDV tSPIR
MSB/LSB in tSPIDV
MOSI (output)
tSPIF master MSB/LSB out master LSB/MSB out
002aaa909
Fig 44. SPI master timing (CPHA = 1)
SS
tSPIF tSPILEAD SPICLK (CPOL = 0) (input) tSPIF SPICLK (CPOL = 1) (input) tSPIA tSPIOH tSPIDV MISO (output) tSPIF
TSPICYC tSPICLKH tSPICLKL tSPIR tSPILAG
tSPIR
tSPICLKL
tSPIR tSPICLKH
tSPIOH tSPIDV
tSPIOH
tSPIDIS
slave MSB/LSB out
slave LSB/MSB out
not defined
tSPIDSU MOSI (input)
tSPIDH
tSPIDSU
tSPIDSU
tSPIDH
MSB/LSB in
LSB/MSB in
002aaa910
Fig 45. SPI slave timing (CPHA = 0)
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SS tSPIF tSPILEAD SPICLK (CPOL = 0) (input) tSPIF SPICLK (CPOL = 1) (input) tSPIOH tSPIDV tSPIA MISO (output) not defined slave MSB/LSB out slave LSB/MSB out tSPICLKL tSPIR tSPICLKH tSPIF tSPICLKH tSPIR tSPIR tSPILAG
TSPICYC tSPICLKL
tSPIOH tSPIDV
tSPIOH tSPIDV tSPIDIS
tSPIDSU MOSI (input)
tSPIDH
tSPIDSU
tSPIDH
MSB/LSB in
LSB/MSB in
002aaa911
Fig 46. SPI slave timing (CPHA = 1)
11.2 ISP entry mode
Table 16. Dynamic characteristics, ISP entry mode VDD = 2.4 V to 3.6 V, unless otherwise specified. Tamb = -40 C to +85 C for industrial applications, -40 C to +125 C extended, unless otherwise specified. Symbol tVR tRH tRL Parameter VDD active to RST active delay time RST HIGH time RST LOW time Conditions pin RST pin RST pin RST Min 50 1 1 Typ Max 32 Unit s s s
VDD tVR RST tRL
002aaa912
tRH
Fig 47. ISP entry waveform
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12. Other characteristics
12.1 Comparator electrical characteristics
Table 17. Comparator electrical characteristics VDD = 2.4 V to 3.6 V, unless otherwise specified. Tamb = -40 C to +85 C for industrial applications, -40 C to +125 C extended, unless otherwise specified. Symbol VIO VIC CMRR tres(tot) t(CE-OV) ILI
[1]
Parameter input offset voltage common-mode input voltage common-mode rejection ratio total response time chip enable to output valid time input leakage current
Conditions
Min 0
[1]
Typ 250 -
Max 10 VDD - 0.3 -50 500 10 1
Unit mV V dB ns s A
-
0 V < VI < VDD
-
This parameter is characterized, but not tested in production.
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12.2 ADC/PGA/temperature sensor electrical characteristics
Table 18. ADC/PGA/temperature sensor electrical characteristics VDD = 2.4 V to 3.6 V, unless otherwise specified. Tamb = -40 C to +85 C for industrial applications, -40 C to +125 C extended, unless otherwise specified. All limits valid for an external source impedance of less than 10 k. Symbol VIA Cia ED EL(adj) EO EG Eu(tot) MCTC ct(port) SRin Tcy(ADC) tADC PGA ts(PGA) GPGA PGA settling time PGA gain within accuracy of ADC G=1 G=2 G=4 G=8 G = 16 tstartup Voffset(O)(nom) Vsen TC tstartup start-up time nominal output offset voltage sensor voltage temperature coefficient start-up time Tamb = +25 C 0.95 1.87 3.70 7.22 14.38 1.00 1.97 3.89 7.60 15.14 100 570 11 200 1 1.05 2.07 4.08 7.98 15.90 2 s V/V V/V V/V V/V V/V s mV mV mV/C s Parameter analog input voltage analog input capacitance differential linearity error integral non-linearity offset error gain error total unadjusted error channel-to-channel matching crosstalk between port inputs input slew rate ADC clock cycle time ADC conversion time ADC enabled 0 kHz to 100 kHz Conditions Min 111 Typ Max VDD + 0.4 15 1 1 2 1 2 1 -60 100 2000 13Tcy(ADC) Unit V pF LSB LSB LSB % LSB LSB dB V/ms ns s VSS - 0.4 -
temperature sensor
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start trigger
adc_clk
1
2
3
4
5
6
7
8
9
10
11
12
13
clk
serial_data_out
D7
D6
D5
D4
D3
D2
D1
D0
ADCDATA_REG
ADCDATA
002aae371
Fig 48. ADC conversion timing
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offset error EO 255
gain error EG
254
253
252
(2)
7 code out 6
(1)
5
4
3
2
1
1 LSB (ideal) 253 254 255 256
0 1 offset error EO 2 3 4 5 6 7 VIA (LSBideal) 1 LSB =
VDDA - VSSA 256
002aae372
(1) Example of an actual transfer curve. (2) The ideal transfer curve.
Fig 49. ADC characteristics
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13. Package outline
PLCC28: plastic leaded chip carrier; 28 leads SOT261-2
eD y X
eE
25
19 18 ZE
A
bp b1 wM
26
28
1
pin 1 index e k 5 e D HD 11 ZD B 4 12
E
HE A A4 A1 (A 3) Lp detail X
vM A
vMB
0
5 scale
10 mm
DIMENSIONS (mm dimensions are derived from the original inch dimensions) A4 A1 b1 D(1) E(1) bp A3 eD eE e HD UNIT A max. min.
mm inches 4.57 4.19 0.51 0.25 0.01 3.05 0.12 0.53 0.33 0.81 0.66
HE
k
Lp
1.44 1.02
v
0.18
w
0.18
y
0.1
ZD(1) ZE(1) max. max.
2.16 2.16
10.92 10.92 12.57 12.57 1.22 11.58 11.58 1.27 9.91 9.91 12.32 12.32 1.07 11.43 11.43 0.43 0.39 0.43 0.39
45 o
0.180 0.02 0.165
0.021 0.032 0.456 0.456 0.05 0.013 0.026 0.450 0.450
0.495 0.495 0.048 0.057 0.007 0.007 0.004 0.085 0.085 0.485 0.485 0.042 0.040
Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT261-2 REFERENCES IEC 112E08 JEDEC MS-018 JEITA EDR-7319 EUROPEAN PROJECTION
ISSUE DATE 99-12-27 01-11-15
Fig 50. PLCC28 package outline (SOT261-2)
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TSSOP28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm
SOT361-1
D
E
A
X
c y HE vMA
Z
28
15
Q A2 pin 1 index A1 (A 3) A
Lp L detail X
1
e bp
14
wM
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 9.8 9.6 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.8 0.5 8 o 0
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT361-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19
Fig 51. TSSOP package outline (SOT361-1)
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14. Abbreviations
Table 19. Acronym ADC CPU CCU CRC DAC EPROM EEPROM EMI LSB MSB PGA PLL PWM RAM RC RTC SAR SFR SPI UART WDT Abbreviations Description Analog to Digital Converter Central Processing Unit Capture/Compare Unit Cyclic Redundancy Check Digital to Analog Converter Erasable Programmable Read-Only Memory Electrically Erasable Programmable Read-Only Memory Electro-Magnetic Interference Least Significant Bit Most Significant Bit Programmable Gain Amplifier Phase-Locked Loop Pulse Width Modulator Random Access Memory Resistance-Capacitance Real-Time Clock Successive Approximation Register Special Function Register Serial Peripheral Interface Universal Asynchronous Receiver/Transmitter WatchDog Timer
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15. Revision history
Table 20. Revision history Release date 20110110 Data sheet status Product data sheet Change notice Supersedes P89LPC9331_9341_9 351_ 9361 v.4 Document ID P89LPC9331_9341_9351_ 9361 v.5 Modifications: P89LPC9331_9341_9351_ 9361 v.4 P89LPC9331_9341_9351_ 9361 v.3 P89LPC9351 v.1
* *
Table 12 "Static characteristics": Added VPOR. Section 7.19 "Reset": Added sentence "When this pin functions as a reset input...". Product data sheet Product data sheet Product data sheet Preliminary data sheet P89LPC9331_9341_9 351_ 9361 v.3 P89LPC9331_9341_ 9351 v.2 P89LPC9351 v.1 -
20100910 20090602
P89LPC9331_9341_9351 v.2 20090505 20081119
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16. Legal information
16.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification -- The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.
malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer's sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer's applications and products planned, as well as for the planned application and use of customer's third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer's applications or products, or the application or use by customer's third party customer(s). Customer is responsible for doing all necessary testing for the customer's applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer's third party customer(s). NXP does not accept any liability in this respect. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.
(c) NXP B.V. 2011. All rights reserved.
16.3 Disclaimers
Limited warranty and liability -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors' aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or
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own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors' standard warranty and NXP Semiconductors' product specifications.
Non-automotive qualified products -- Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors' warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors' specifications such use shall be solely at customer's
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V.
17. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
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18. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 2.1 Principal features . . . . . . . . . . . . . . . . . . . . . . . 1 2.2 Additional features . . . . . . . . . . . . . . . . . . . . . . 2 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 3.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 5 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 6 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8 7 Functional description . . . . . . . . . . . . . . . . . . 12 7.1 Special function registers . . . . . . . . . . . . . . . . 12 7.2 Enhanced CPU . . . . . . . . . . . . . . . . . . . . . . . . 30 7.3 Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.3.1 Clock definitions . . . . . . . . . . . . . . . . . . . . . . . 30 7.3.2 CPU clock (OSCCLK). . . . . . . . . . . . . . . . . . . 30 7.4 Crystal oscillator option. . . . . . . . . . . . . . . . . . 30 7.4.1 Low speed oscillator option . . . . . . . . . . . . . . 30 7.4.2 Medium speed oscillator option . . . . . . . . . . . 30 7.4.3 High speed oscillator option . . . . . . . . . . . . . . 30 7.5 Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.6 On-chip RC oscillator option . . . . . . . . . . . . . . 31 7.7 Watchdog oscillator option . . . . . . . . . . . . . . . 31 7.8 External clock input option . . . . . . . . . . . . . . . 31 7.9 Clock source switching on the fly . . . . . . . . . . 31 7.10 CCLK wake-up delay . . . . . . . . . . . . . . . . . . . 32 7.11 CCLK modification: DIVM register . . . . . . . . . 32 7.12 Low power select . . . . . . . . . . . . . . . . . . . . . . 32 7.13 Memory organization . . . . . . . . . . . . . . . . . . . 33 7.14 Data RAM arrangement . . . . . . . . . . . . . . . . . 33 7.15 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.15.1 External interrupt inputs . . . . . . . . . . . . . . . . . 34 7.16 I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.16.1 Port configurations . . . . . . . . . . . . . . . . . . . . . 36 7.16.1.1 Quasi-bidirectional output configuration . . . . . 36 7.16.1.2 Open-drain output configuration . . . . . . . . . . . 36 7.16.1.3 Input-only configuration . . . . . . . . . . . . . . . . . 37 7.16.1.4 Push-pull output configuration . . . . . . . . . . . . 37 7.16.2 Port 0 analog functions . . . . . . . . . . . . . . . . . . 37 7.16.3 Additional port features. . . . . . . . . . . . . . . . . . 37 7.17 Power monitoring functions . . . . . . . . . . . . . . 37 7.17.1 Brownout detection . . . . . . . . . . . . . . . . . . . . . 38 7.17.2 Power-on detection. . . . . . . . . . . . . . . . . . . . . 38 7.18 Power reduction modes . . . . . . . . . . . . . . . . . 38 7.18.1 Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.18.2 Power-down mode . . . . . . . . . . . . . . . . . . . . . 38 7.18.3 7.19 7.19.1 7.20 7.20.1 7.20.2 7.20.3 7.20.4 7.20.5 7.20.6 7.21 7.22 7.22.1 7.22.2 7.22.3 7.22.4 7.22.5 7.22.6 7.22.7 7.22.8 7.22.9 7.23 7.23.1 7.23.2 7.23.3 7.23.4 7.23.5 7.23.6 7.23.7 7.23.8 7.23.9 7.23.10 7.24 7.25 7.25.1 7.26 7.26.1 7.26.2 7.26.3 7.27 7.28 7.29 7.29.1 7.29.2 7.29.3 7.30 Total Power-down mode . . . . . . . . . . . . . . . . Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset vector. . . . . . . . . . . . . . . . . . . . . . . . . . Timers/counters 0 and 1 . . . . . . . . . . . . . . . . Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer overflow toggle output . . . . . . . . . . . . . RTC/system timer . . . . . . . . . . . . . . . . . . . . . CCU (P89LPC9351/9361) . . . . . . . . . . . . . . . CCU clock . . . . . . . . . . . . . . . . . . . . . . . . . . . CCUCLK prescaling. . . . . . . . . . . . . . . . . . . . Basic timer operation . . . . . . . . . . . . . . . . . . . Output compare . . . . . . . . . . . . . . . . . . . . . . . Input capture . . . . . . . . . . . . . . . . . . . . . . . . . PWM operation . . . . . . . . . . . . . . . . . . . . . . . Alternating output mode. . . . . . . . . . . . . . . . . PLL operation. . . . . . . . . . . . . . . . . . . . . . . . . CCU interrupts . . . . . . . . . . . . . . . . . . . . . . . . UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Baud rate generator and selection. . . . . . . . . Framing error . . . . . . . . . . . . . . . . . . . . . . . . . Break detect. . . . . . . . . . . . . . . . . . . . . . . . . . Double buffering. . . . . . . . . . . . . . . . . . . . . . . Transmit interrupts with double buffering enabled (modes 1, 2 and 3) . . . . . . . . . . . . . . The 9th bit (bit 8) in double buffering (modes 1, 2 and 3). . . . . . . . . . . . . . . . . . . . . I2C-bus serial interface. . . . . . . . . . . . . . . . . . SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical SPI configurations . . . . . . . . . . . . . . . Analog comparators . . . . . . . . . . . . . . . . . . . . Internal reference voltage . . . . . . . . . . . . . . . Comparator interrupt . . . . . . . . . . . . . . . . . . . Comparators and power reduction modes . . . KBI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . Additional features . . . . . . . . . . . . . . . . . . . . . Software reset . . . . . . . . . . . . . . . . . . . . . . . . Dual data pointers . . . . . . . . . . . . . . . . . . . . . Data EEPROM (P89LPC9351/9361) . . . . . . . Flash program memory . . . . . . . . . . . . . . . . . 39 39 40 40 40 40 40 40 40 41 41 41 41 41 41 42 42 42 43 43 44 44 44 45 45 45 45 45 46 46 46 46 46 49 50 51 52 53 53 53 54 54 54 54 55 55
continued >>
P89LPC9331_9341_9351_9361
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 -- 10 January 2011
93 of 94
NXP Semiconductors
P89LPC9331/9341/9351/9361
8-bit microcontroller with accelerated two-clock 80C51 core
55 55 56 56 56 56 56 57 57 58 58 58 58 58 58 60 61 61 62 62 62 62 62 62 63 63 63 63 63 63 63 64 64 64 65 66 68 72 75 76 80 82 83 83 84 87 14 15 16 16.1 16.2 16.3 16.4 17 18 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 90 91 91 91 91 92 92 93
7.30.1 General description . . . . . . . . . . . . . . . . . . . . 7.30.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.30.3 Flash organization . . . . . . . . . . . . . . . . . . . . . 7.30.4 Using flash as data storage . . . . . . . . . . . . . . 7.30.5 Flash programming and erasing . . . . . . . . . . . 7.30.6 ICP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.30.7 IAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.30.8 ISP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.30.9 Power-on reset code execution . . . . . . . . . . . 7.30.10 Hardware activation of the bootloader . . . . . . 7.31 User configuration bytes . . . . . . . . . . . . . . . . . 7.32 User sector security bytes . . . . . . . . . . . . . . . 8 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1 General description . . . . . . . . . . . . . . . . . . . . 8.2 Features and benefits . . . . . . . . . . . . . . . . . . . 8.3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . 8.4 PGA (P89LPC9351/9361) . . . . . . . . . . . . . . . 8.5 Temperature sensor . . . . . . . . . . . . . . . . . . . . 8.6 ADC operating modes . . . . . . . . . . . . . . . . . . 8.6.1 Fixed channel, single conversion mode . . . . . 8.6.2 Fixed channel, continuous conversion mode . 8.6.3 Auto scan, single conversion mode . . . . . . . . 8.6.4 Auto scan, continuous conversion mode . . . . 8.6.5 Dual channel, continuous conversion mode . . 8.6.6 Single step mode . . . . . . . . . . . . . . . . . . . . . . 8.7 Conversion start modes . . . . . . . . . . . . . . . . . 8.7.1 Timer triggered start . . . . . . . . . . . . . . . . . . . . 8.7.2 Start immediately . . . . . . . . . . . . . . . . . . . . . . 8.7.3 Edge triggered . . . . . . . . . . . . . . . . . . . . . . . . 8.7.4 Dual start immediately . . . . . . . . . . . . . . . . . . 8.8 Boundary limits interrupt . . . . . . . . . . . . . . . . . 8.9 DAC output to a port pin with high output impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.10 Clock divider . . . . . . . . . . . . . . . . . . . . . . . . . . 8.11 Power-down and Idle mode . . . . . . . . . . . . . . 9 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 10 Static characteristics. . . . . . . . . . . . . . . . . . . . 10.1 Current characteristics . . . . . . . . . . . . . . . . . . 10.2 Internal RC/watchdog oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 10.3 BOD characteristics . . . . . . . . . . . . . . . . . . . . 11 Dynamic characteristics . . . . . . . . . . . . . . . . . 11.1 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 ISP entry mode . . . . . . . . . . . . . . . . . . . . . . . . 12 Other characteristics . . . . . . . . . . . . . . . . . . . . 12.1 Comparator electrical characteristics . . . . . . . 12.2 ADC/PGA/temperature sensor electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 13 Package outline . . . . . . . . . . . . . . . . . . . . . . . .
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2011.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 10 January 2011 Document identifier: P89LPC9331_9341_9351_9361

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